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DP-HLS: Dynamic Programming FPGA Acceleration using High-Level Synthesis

Table of Contents

Overview

We plan to accelerate and implement major important algorithms based on dynamic programming used in Bioinformatics applications. User can configure the parameterizable kernels as per their usecase to be implemented on an FPGA device.

Getting Started

How to use

Modify the parameters in params.h file as per your use-case before running our code. Currently our code generates random query and reference sequences as the inputs. You can configure this by reading the sequences from an input file in seq_align_test.cpp

Create a project in Xilinx Vitis HLS tool and select our code as source files. Select a device and clock frequency, then synthesize the code. Follow the steps for synthesizing the code from their documentation.

Results

Currently our code performs local sequence alignment using Smith Waterman algorithm with affine gap penalty (we do not perform traceback now. Support for traceback will be added soon)

HLS Tool: Xilinx Vitis HLS
Device: Zynq UltraScale+ MPSoC (xczu7ev-ffvc1156-2-i)
Frequency: 250 MHz
Length of the reference sequence (ref_length): 1024
Length of the query sequence (query_length): 1024
Number of Processing Elements (PE): 32
Data type: 16 bit fixed point
Number of kernels in parallel (N_BLOCKS): 8

Following is the table summarizing the resource usage with various set of sequence alignment algorithms:

Sequence Alignment Algorithms Gap Penalty Banding Resource Utilization
FF LUT BRAM
Smith Waterman Linear Non Banded
Banded
Affine Non Banded 16590 47526 144
Banded
Needleman Wunsch Linear 0
Affine

References