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<title>Process Bus Timing Lab - PTP Lab Clock Simulator for IEC 61850 FAT/SAT</title>
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<metaname="description" content="Process Bus Timing Lab is a free Apache-2.0 Windows PTPv2 Layer-2 lab clock simulator and passive timing-health monitor for IEC 61850 Process Bus FAT, SAT, analyzer validation, VLAN/QinQ visibility, and controlled timing scenarios." />
<title>Process Bus Timing Lab - Windows PTP Simulator and Timing Monitor for IEC 61850</title>
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<metaname="description" content="Process Bus Timing Lab is a Windows PTP lab simulator and timing-health monitor for IEC 61850 FAT, SAT, analyzer validation, VLAN/QinQ visibility, RAW NIC self-test, and Process Bus troubleshooting." />
<metaproperty="og:description" content="A Windows-friendly PTPv2 Layer-2 lab simulator and timing-health monitor for IEC 61850 Process Bus engineering workflows." />
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<metaproperty="og:title" content="Process Bus Timing Lab - PTP Simulator and Timing Monitor" />
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<metaproperty="og:description" content="Windows PTP lab simulator and timing-health monitor for IEC 61850 FAT, SAT, analyzer validation, and Process Bus troubleshooting." />
"Passive PTP monitor grouped by domain and source",
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"Timing-health evidence export"
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"VLAN and QinQ PTP validation",
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"Scenario player for analyzer diagnostics",
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"PDF and ZIP timing evidence export"
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"description": "Free Apache-2.0 Windows tool for controlled PTPv2 visibility checks, analyzer validation, passive timing-health symptoms, and evidence export in IEC 61850 Process Bus lab networks."
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"description": "Windows PTP lab simulator and timing-health monitor for IEC 61850 FAT, SAT, analyzer validation, VLAN/QinQ visibility, RAW NIC self-test, and Process Bus troubleshooting."
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</head>
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<divclass="header-shell">
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<aclass="brand" href="#top" aria-label="Process Bus Timing Lab home">
<pclass="eyebrow"><spanclass="material-symbols-rounded">bolt</span> IEC 61850 Process Bus · PTPv2 Layer-2 · Apache-2.0</p>
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<h1>Make PTP visibility clear before SV and GOOSE testing becomes guesswork.</h1>
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<pclass="lead">A Windows-friendly lab simulator and passive timing monitor for engineers validating PTP presence, VLAN/QinQ handling, analyzer decoding, Pdelay behavior, and timing-health evidence during FAT, SAT, commissioning preparation, and lab troubleshooting.</p>
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<pclass="eyebrow"><spanclass="material-symbols-rounded">verified</span> IEC 61850 Process Bus · PTPv2 Layer-2 · Apache-2.0</p>
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<h1>PTP visibility for engineers who need answers before Process Bus testing goes blind.</h1>
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<pclass="lead">Process Bus Timing Lab is a Windows PTP lab simulator and timing-health monitor for IEC 61850 FAT, SAT, analyzer validation, and Process Bus troubleshooting. Use it to validate PTP visibility, VLAN/QinQ paths, analyzer decoding, and controlled timing symptoms before deeper SV and GOOSE testing.</p>
<span>PTPv2 Layer-2</span><span>VLAN / QinQ</span><span>RAW NIC self-test</span><span>Timing health</span>
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</div>
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<pclass="safety-note"><strong>Safety boundary:</strong>this is a lab simulator and diagnostic companion. It is not a GPS grandmaster, certified timing source, hardware-timestamped clock, or relay-acceptance timing reference.</p>
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<pclass="safety-note"><strong>Safety boundary:</strong>built for lab visibility and analyzer validation. It is not a certified grandmaster, GPS clock, hardware-timestamped timing source, or relay-acceptance reference.</p>
<article><span>01</span><strong>See timing traffic</strong><p>Confirm Layer-2 PTP visibility on the selected NIC before analyzer work starts.</p></article>
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<article><span>02</span><strong>Validate decoding</strong><p>Generate controlled Announce, Sync, Follow_Up, and Pdelay patterns.</p></article>
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<article><span>03</span><strong>Check VLAN path</strong><p>Exercise untagged, VLAN, and QinQ PTP frame handling.</p></article>
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<article><span>04</span><strong>Export evidence</strong><p>Keep short reports and session packages for engineering discussion.</p></article>
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<article><span>04</span><strong>Export evidence</strong><p>Keep short timing-health reports for FAT/SAT notes and engineering discussion.</p></article>
<pclass="eyebrow"><spanclass="material-symbols-rounded">rocket_launch</span> Download and run</p>
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<h2>Portable Windows packages for lab engineers.</h2>
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<p>Use the WPF dashboard for guided sessions or the CLI for repeatable RAW self-test, protocol smoke validation, passive monitor, and evidence export.</p>
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<h2>Portable Windows EXE packages for lab engineers.</h2>
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<p>Use the WPF dashboard for guided sessions or the CLI for repeatable protocol smoke validation, adapter listing, RAW self-test, passive monitor, and evidence export.</p>
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</div>
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<divclass="download-cards">
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<ahref="https://github.com/masarray/PtpLabClock/releases" class="download-card"><spanclass="material-symbols-rounded">desktop_windows</span><strong>Windows desktop app</strong><small>Self-contained release package for easiest use.</small></a>
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<ahref="https://github.com/masarray/PtpLabClock/releases" class="download-card"><spanclass="material-symbols-rounded">terminal</span><strong>Console tool</strong><small>Protocol validation, adapter list, RAW self-test, and scripts.</small></a>
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<ahref="https://github.com/masarray/PtpLabClock/blob/master/docs/quick-start.md" class="download-card"><spanclass="material-symbols-rounded">menu_book</span><strong>Quick start</strong><small>Install Npcap, select NIC, run validation, and inspect Wireshark.</small></a>
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<ahref="https://github.com/masarray/PtpLabClock/releases" class="download-card"><spanclass="material-symbols-rounded">desktop_windows</span><strong>Desktop portable EXE</strong><small>Run the WPF timing dashboard without opening Visual Studio.</small></a>
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<ahref="https://github.com/masarray/PtpLabClock/releases" class="download-card"><spanclass="material-symbols-rounded">terminal</span><strong>Console portable EXE</strong><small>Use CLI validation, RAW self-test, and scriptable lab checks.</small></a>
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<ahref="https://github.com/masarray/PtpLabClock/blob/master/docs/quick-start.md" class="download-card"><spanclass="material-symbols-rounded">menu_book</span><strong>Quick start</strong><small>Install Npcap, select a NIC, run self-test, and inspect Wireshark.</small></a>
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</div>
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</section>
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<sectionclass="section" id="features">
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<divclass="section-heading reveal">
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<pclass="eyebrow"><spanclass="material-symbols-rounded">hub</span> Built for practical timing checks</p>
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<h2>Focused PTP tools without hiding the field limitations.</h2>
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<p>The goal is fast visibility, repeatable lab stimuli, passive health symptoms, and honest wording. Windows software timestamps are useful for diagnostics, not for certified time distribution.</p>
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<pclass="eyebrow"><spanclass="material-symbols-rounded">hub</span> Built for practical Process Bus timing checks</p>
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<h2>Turn hidden timing assumptions into visible engineering evidence.</h2>
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<p>The product focuses on early visibility, repeatable lab stimuli, passive timing-health symptoms, and honest field boundaries. Windows software capture is useful for diagnostics, not certified time distribution.</p>
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</div>
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<divclass="feature-grid">
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<articleclass="feature-card reveal"><b>PTP serializer</b><h3>Protocol-grade frames</h3><p>Announce, Sync, Follow_Up, Pdelay_Req, Pdelay_Resp, and Pdelay_Resp_Follow_Up for controlled analyzer validation.</p></article>
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<articleclass="feature-card reveal delay-1"><b>Ethernet</b><h3>VLAN and QinQ aware</h3><p>Frame builders and inspectors cover untagged, IEEE 802.1Q VLAN, and stacked-tag lab scenarios.</p></article>
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<articleclass="feature-card reveal delay-2"><b>Monitor</b><h3>Passive timing view</h3><p>Group observed PTP by domain, source clock identity, sequence behavior, and message pairing symptoms.</p></article>
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<articleclass="feature-card reveal"><b>Health</b><h3>Explainable checks</h3><p>Surface missing Follow_Up, GM-loss scenario, sequence jump, degraded quality, and stale timing symptoms.</p></article>
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<articleclass="feature-card reveal delay-1"><b>RAW NIC</b><h3>Npcap boundary</h3><p>Adapter list, MAC-aware source identity, VLAN-aware filter, and a RAW self-test before lab publication.</p></article>
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<articleclass="feature-card reveal delay-2"><b>Evidence</b><h3>Report package</h3><p>Export concise PDF and ZIP evidence for issue discussion, FAT notes, or analyzer validation records.</p></article>
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<articleclass="feature-card reveal"><b>PTP simulator</b><h3>Controlled Layer-2 frames</h3><p>Generate Announce, Sync, Follow_Up, Pdelay_Req, Pdelay_Resp, and Pdelay_Resp_Follow_Up patterns for analyzer validation.</p></article>
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<articleclass="feature-card reveal delay-1"><b>Ethernet</b><h3>VLAN and QinQ aware</h3><p>Build and inspect untagged, IEEE 802.1Q VLAN, and stacked-tag PTP paths used in Process Bus lab networks.</p></article>
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<articleclass="feature-card reveal delay-2"><b>Monitor</b><h3>Passive timing-health view</h3><p>Group observed PTP by domain, source clock identity, sequence behavior, and message-pairing symptoms.</p></article>
<articleclass="feature-card reveal delay-1"><b>RAW NIC</b><h3>Npcap boundary</h3><p>Adapter list, MAC-aware source identity, VLAN-aware capture filter, and RAW self-test before lab publication.</p></article>
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<articleclass="feature-card reveal delay-2"><b>Evidence</b><h3>Reports for discussion</h3><p>Export concise PDF and ZIP evidence for issue discussion, FAT notes, SAT preparation, or analyzer validation records.</p></article>
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</div>
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</section>
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<sectionclass="section screenshot-section">
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<divclass="section-heading reveal">
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<pclass="eyebrow"><spanclass="material-symbols-rounded">dashboard</span> Real product workflow</p>
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<h2>Clock profile, live flow, scenarios, VLAN, and health in one workspace.</h2>
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<p>The desktop workspace is designed for engineers who need to see what the timing layer is doing without jumping between packet dumps, handwritten notes, and generic counters.</p>
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</div>
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<figureclass="wide-shot reveal delay-1">
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<imgsrc="assets/ptp-lab-dashboard.svg" alt="Process Bus Timing Lab dashboard with clock profile, live timing flow, scenario player, and timing health diagnostics" />
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<figcaption>Dashboard preview for IEC 61850 Process Bus timing visibility, analyzer validation, and lab scenario testing.</figcaption>
<div><span>5</span><h3>Export evidence</h3><p>Save session report and attach it to engineering notes or analyzer issue reports.</p></div>
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</main>
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<footerclass="site-footer">
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<div><strong>Process Bus Timing Lab</strong><span>PTP lab clock simulator and timing-health monitor for IEC 61850 engineering workflows.</span></div>
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<div><strong>Process Bus Timing Lab</strong><span>Windows PTP lab simulator and timing-health monitor for IEC 61850 FAT, SAT, analyzer validation, and Process Bus troubleshooting.</span></div>
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