This tutorial goes through the steps of generating a basic XDMA and DDR4 Block Diagram Design in Vivado for the XCKU15P FPGA in the Innova-2.
The XDMA Communication notes have newer and simpler design instructions.
The innova2_8gb_adlt_xdma_ddr4_demo project is a more refined and tested implementation of everything in these notes.
Under Linux, start Vivado with:
sudo /tools/Xilinx/Vivado/2021.2/bin/vivado
Create Project
Choose directory and project name.
No source files are needed to start.
Select the target FPGA, in this case the xcku15p-ffve1517-2-i.
Project Summary.
Click on Create Block Design in the Flow Navigator and give it a name.
In the Diagram editor window, click Add IP and search for xdma. Double-click DMA/Bridge Subsystem for PCI Express.
Under the Basic tab in XDMA Customization, choose X0Y2 as the PCIe Block Location, X8 as the Lane Width, 8.0 GT/s as the Maximum Link Speed, and AXI Memory Mapped as the DMA Interface Option. The actual pins are defined later. This selects which PCIe Block will be controlling the Gigabit GTY SERDES Transceivers. All other options can be left at their defaults.
Under the PCIe ID tab, choose Memory controller as the Base Class Menu and Other memory controller as the Sub Class Interface Menu.
Under the Miscellaneous tab, uncheck Configuration Management Interface to disable it.
Under the DMA tab, select 4 as the number of DMA Read and Write Channels. Click OK to update the design in the Block Diagram.
Click Run Block Automation in the Diagram editor.
Choose the same options as earlier for the IP Level design; X8, 8.0 GT/s, AXI Memory Mapped, 4 Read and Write Channels.
Block Automation will generate an appropriate buffer for the clock and add external signals.
In the Diagram editor window, click Add IP and search for axi smart. Double-click AXI SmartConnect. SmartConnect automates clock and reset connections between AXI Slave and Master devices and communication among them.
This design will require 1 Slave interface, 4 Master interfaces, 2 clock inputs, and 1 asynchronous reset.
Connect the XDMA and AXI SmartConnect blocks in the Diagram Editor. M_AXI to S00_AXI and axi_clk to aclk.
In the Diagram editor window, click Add IP and search for ddr4. Double-click DDR4 SDRAM (MIG). This is the DDR4 Memory Interface Generator.
Under the Basic tab in DDR4 Customization, write 1428 as the Memory Device Interface Speed (ps), choose 9996 (100.04MHz) as the Reference Input Clock Speed (ps), choose MT40A1G16WBU-083E as the Memory Part, choose 64 as the Data Width, and DM NO DBI as the Data Mask and DBI. 1428ps=700MHz=1400MT is slow for DDR4 and a 64-bit width prevents ECC from being enabled. This is meant to be used for testing. The Innova-2 has MT40A1G16KNR-075 ICs with D9WFR FBGA Code that should be able to handle up to 750ps=1333MHz=2666MT. Note parts rated to -083 should be able to handle up to 833ps=1200MHz=2400MT.
Under the AXI Options tab, choose Round Robin as the Arbitration Scheme. Leave all other options at their defaults. Click OK to continue.
Click Run Connection Automation in the Diagram editor.
Select all the ports for automatic connection.
This will generate a Processor System Reset Block that controls the Active-Low Asynchronous Reset (aresetn) for the design. Connect peripheral_aresetn[0:0] to c0_ddr4_aresetn and AXI SmartConnect aresetn. The peripheral reset and DDR4 UI Clock will be used for all the AXI blocks.
Connect the DDR4 User Interface Clock (c0_ddr4_ui_clk) to AXI SmartConnect aclk1. This will be the slowest clock in the design at 100MHz.
Block automation generated reset_rtl_0_0 for System Reset (sys_rst) for the DDR4 Block but the Innova-2 does not have such a signal.
Delete the DDR4 System Reset (sys_rst) signal and port (reset_rtl_0_0). A DDR4 reset signal will be added next.
In the Diagram editor window, click Add IP and search for vector. Double-click Utility Vector Logic to add a basic inverter gate.
Choose a bit width (C_SIZE) of 1 and the C_OPERATION as not.
Invert the the PCIe Reset Signal (reset_rtl_0) and connect it to the DDR4 System Reset (sys_rst). PCIe Reset is Active-Low while DDR4 Reset is Active-High. Both blocks are thus enabled when the board is powered-on and PCIe activated.
In the Diagram editor window, click Add IP and search for counter. Double-click Binary Counter. This Binary Counter will connect to the XDMA Clock and blink an LED about once per second.
Set the Output Width as 28. XDMA uses a 250MHz AXI Interface clock so 250000000/(2^28)~=0.9313Hz
Connect the counter CLK input to XDMA axi_aclk.
Only the 28th bit will be needed for the Status LED. In the Diagram editor window, click Add IP and search for slice. Double-click Slice. The Slice block selects specified bits from a wide bus.
Customize the Slice Block to output the last bit, 27, from the 28-Bit Wide input.
Connect the Counter Output (Q[27:0]) to Slice Input (Din[27:0]). Note the widths match.
Right-click on the Slice Dout[0:0] output and choose Make External.
This will create an external port for the blinking XDMA Status LED.
In the Diagram editor window, click Add IP and search for gpio. Double-click AXI GPIO. This GPIO will be used to read status signals over AXI.
Customize the GPIO for All Inputs with a GPIO Width of 8.
Most status-related signals in the design are single wires while the GPIO Block expects a bus. In the Diagram editor window, click Add IP and search for concat. Double-click Concat to allow concatenating individual signals into a bus.
Customize the Concat Block into eight 1-Bit wide inputs.
Click the Plus Sign on the GPIO Block to expand the signal port.
Connect the Concat Output (dout[7:0]) to the GPIO Input (gpio_io_i[7:0]).
Connect the XDMA Link Up signal (user_lnk_up) to the Concat block. This is useless as XDMA must be working to access the GPIO but it is a simple sanity check.
Connect the DDR4 Calibration Complete signal (c0_init_calib_complete) to the Concat block.
Connect the GPIO Block (S_AXI) to the SmartConnect Block (M01_AXI). Use SmartConnect aclk for axi_aclk and SmartConnect aresetn for s_axi_aresetn.
In the Diagram editor window, click Add IP and search for gpio. Double-click AXI GPIO.
Customize the GPIO for All Outputs with a GPIO Width of 1. Set the Default Output Value to 0x00000000. The Innova-2 has inverted LED outputs which means the LED will be ON with a value of 0.
Right-click on GPIO and choose Make External.
Vivado should generate a GPIO_0 port.
Connect the GPIO Block (S_AXI) to the SmartConnect Block (M02_AXI). Use SmartConnect aclk1 for s_axi_aclk and SmartConnect aresetn for s_axi_aresetn. The picture below is wrong, aclk1, the 100MHz clock, is to be used for the AXI Blocks.
In the Diagram editor window, click Add IP and search for axi bram. Double-click AXI BRAM Controller. BRAM is FPGA Fabric Memory and is useful here as a functionality check.
Customize the BRAM Controller to a Data Width of 1024 and 1 BRAM Interfaces.
Connect the BRAM Controller Block (S_AXI) to the SmartConnect Block (M03_AXI). Use SmartConnect aclk1 for axi_aclk and SmartConnect aresetn for axi_aresetn.
Run Connection Automation.
It should generate a Block Memory Generator Block.
The Block Design is now complete. Note all the AXI Blocks use the DDR4 User Interface Clock. At 100MHz it is slower than the 250MHz XDMA Clock. This makes it easier to meet timing constraints.
Open the Address Editor tab. Right-click and choose Assign All. These are the addresses at which the AXI Blocks will be accessed over XDMA. Make sure there are no overlaps.
Back in the Diagram editor, click Validate Design.
This should take about a minute and complete with no errors.
Open the Sources tab and click Add Sources. If you already have a constraints file then add it here.
Add or create constraints
Create File
Create an XDC (Xilinx Design Constraints) file.
Finish Constraints File Creation.
Double-click the file to open the text editor.
Add Memory Configuration constraints for the bitstream file.
Note all the external signal ports in the Block diagram. Left side has system inputs and signals that control your design. Right side has system outputs and bidirectional IO controlled by your design.
Add PCIe constraints. Rename signals to match the Block design names if necessary. Different versions of Vivado use different default names.
Add GPIO and LED constraints. The Innova-2 has two LEDs.
Add DDR4 constraints.
The Vivado GUI can also be used for Pin Assignment and Configuration Memory Setup.
Open Implemented Design in the Flow Navigator.
Open the IO Ports tab, expand the signal hierarchy and choose pins for the various signals.
When you are finished assigning pins to signals, File->Constraints->Save.
In the Sources tab:
Right-click on the Block Design file and select Create HDL Wrapper:
Allow Vivado to create and manage the HDL Wrapper. This is the top-level HDL file associated with the design and must be included in every project.
The HDL wrapper file will appear in the project's design hierarchy.
Click Generate Bitstream which will Synthesize and Implement the Block design.
After the Bitstream is successfully generated, Write Configuration Memory File.
Select bin, mt25qu512_x1_x2_x4_x8, SPIx8, Load bitstream files, and a location and name for the output binary files. The bitstream will end up, for example, in the DESIGN_NAME/DESIGN_NAME.runs/impl_1 subdirectory as SOMETHING.bit. Vivado will add the _primary.bin and _secondary.bin extensions as the Innova-2 uses dual MT25QU512 FLASH ICs in x8 for high speed programming.
Select the mt25qu512-spi-x1_x2_x4_x8 as the Memory Part.
A Project TCL Script can be used to regenerate a project in Vivado and is useful for version control and distribution of projects.
After generating and testing a bitstream, File->Project->Write TCL.
Open the Project TCL File for editing and search for constraints.xdc.
Shorten the path to $origin_dir/constraints.xdc at the start of the file.
Search for the next instance of constraints.xdc.
Shorten the path appropriately near the middle of the file.
Copy the constraints.xdc file to the same directory as the Project TCL file.
Test your Project's TCL Script by sourceing it in the Vivado Tcl Console.
Under Tools->Settings, change the Project Device.
The project's IP will now be out-of-date. Run Report IP Status.
Select all the IP check boxes and run Upgrade Selected.
The IP should upgrade successfully if it is not too different an FPGA. Note that constraints will also need to be updated if the package has changed.
Rerun IP Status to confirm everything has upgraded.
