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Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'loopback_top'
Design Information
------------------
Command Line : map -intstyle ise -p xc5vlx110t-ff1136-1 -w -logic_opt off -ol
high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr
off -lc off -power off -o loopback_top_map.ncd loopback_top.ngd loopback_top.pcf
Target Device : xc5vlx110t
Target Package : ff1136
Target Speed : -1
Mapper Version : virtex5 -- $Revision: 1.55 $
Mapped Date : Mon Apr 06 14:57:50 2015
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc5vlx110t' is not a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 8 secs
Total CPU time at the beginning of Placer: 7 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:94cb9724) REAL time: 8 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:94cb9724) REAL time: 8 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:94cb9724) REAL time: 8 secs
Phase 4.37 Local Placement Optimization
Phase 4.37 Local Placement Optimization (Checksum:94cb9724) REAL time: 8 secs
Phase 5.33 Local Placement Optimization
Phase 5.33 Local Placement Optimization (Checksum:94cb9724) REAL time: 9 secs
Phase 6.32 Local Placement Optimization
Phase 6.32 Local Placement Optimization (Checksum:94cb9724) REAL time: 9 secs
Phase 7.2 Initial Clock and IO Placement
Phase 7.2 Initial Clock and IO Placement (Checksum:e0625d63) REAL time: 9 secs
Phase 8.36 Local Placement Optimization
Phase 8.36 Local Placement Optimization (Checksum:e0625d63) REAL time: 9 secs
Phase 9.30 Global Clock Region Assignment
Phase 9.30 Global Clock Region Assignment (Checksum:e0625d63) REAL time: 9 secs
Phase 10.3 Local Placement Optimization
Phase 10.3 Local Placement Optimization (Checksum:e0625d63) REAL time: 9 secs
Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:e0625d63) REAL time: 9 secs
Phase 12.8 Global Placement
........
....
Phase 12.8 Global Placement (Checksum:2c9dcd30) REAL time: 10 secs
Phase 13.29 Local Placement Optimization
Phase 13.29 Local Placement Optimization (Checksum:2c9dcd30) REAL time: 10 secs
Phase 14.5 Local Placement Optimization
Phase 14.5 Local Placement Optimization (Checksum:2c9dcd30) REAL time: 10 secs
Phase 15.18 Placement Optimization
Phase 15.18 Placement Optimization (Checksum:2ea0bbc1) REAL time: 14 secs
Phase 16.5 Local Placement Optimization
Phase 16.5 Local Placement Optimization (Checksum:2ea0bbc1) REAL time: 14 secs
Phase 17.34 Placement Validation
Phase 17.34 Placement Validation (Checksum:2ea0bbc1) REAL time: 14 secs
Total REAL time to Placer completion: 14 secs
Total CPU time to Placer completion: 13 secs
Running post-placement packing...
Writing output files...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 60 out of 69,120 1%
Number used as Flip Flops: 60
Number of Slice LUTs: 111 out of 69,120 1%
Number used as logic: 109 out of 69,120 1%
Number using O6 output only: 82
Number using O5 output only: 24
Number using O5 and O6: 3
Number used as exclusive route-thru: 2
Number of route-thrus: 26
Number using O6 output only: 26
Slice Logic Distribution:
Number of occupied Slices: 36 out of 17,280 1%
Number of LUT Flip Flop pairs used: 114
Number with an unused Flip Flop: 54 out of 114 47%
Number with an unused LUT: 3 out of 114 2%
Number of fully used LUT-FF pairs: 57 out of 114 50%
Number of unique control sets: 2
Number of slice register sites lost
to control set restrictions: 4 out of 69,120 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 4 out of 640 1%
Number of LOCed IOBs: 4 out of 4 100%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 32 3%
Number used as BUFGs: 1
Average Fanout of Non-Clock Nets: 3.73
Peak Memory Usage: 580 MB
Total REAL time to MAP completion: 14 secs
Total CPU time to MAP completion: 14 secs
Mapping completed.
See MAP report file "loopback_top_map.mrp" for details.