Uninferrable width on reg after using fromBits

[da-steve101]

class UserMod( bw : Int ) extends Module {
     val io = new Bundle {
       val in = UInt( INPUT, bw )
       val out = UInt( OUTPUT )
     }
     val r = RegNext( UInt( width = io.in.getWidth() ).fromBits(io.in) )
     println( r.getWidth() )
     io.out := r
}

This gives:
Chisel.GetWidthException: getWidth was called on a Register or on an object connected in some way to a Register that has a statically uninferrable width
This is fine however:

class UserMod( bw : Int ) extends Module {
     val io = new Bundle {
       val in = UInt( INPUT, bw )
       val out = UInt( OUTPUT )
     }
     val r = RegNext( io.in )
     println( r.getWidth() )
     io.out := r
}