pld2vect.py

Experimental tool to convert GAL logic definitions into test vectors for the TL866II+ programmer.

Overview

pld2vect.py reads a GAL (Generic Array Logic) device definition file and generates test vectors in a format compatible with the FOSS programmer minipro for the TL866II+ and successors.

Instead of manually writing test vectors to verify programmed GALs, you can use the logic equations in the input file for GALasm or galette, and the tool automatically generates targeted test vectors covering all logic paths — including feedback, tristate outputs, and registered logic.

Features

• Combinational logic — AND, OR, XOR, NOT with arbitrary expressions
• Registered logic — D-type flip-flops with .R extension
• Tristate outputs — .T and .E extensions
• Asynchronous Reset / Synchronous Preset — AR/SP on device level, .ARST/.APRST per output
• Per-output clock control — .CLK extension (including gated clocks like O6.CLK = Clock * O6)
• Combinatorial feedback — outputs referencing other outputs (iterative solver)
• Active-low pins — both inputs (/I1) and outputs (/O4)
• VCC/GND constants — usable in expressions
• Multi-line equations — continuation lines with trailing operators
• Inline comments — ; comment delimiter
• Output validation — warns about undefined identifiers or missing tristate pairs

Supported Devices

The tool is GAL-family agnostic — it works with any device definition following the syntax for:

• GAL16V8
• GAL20V8
• GAL22V10
• GAL20RA10
• other similar devices

The pin count and layout are part of the definition file, not hardcoded.

Compatibility

pld2vect.py accepts .pld files written for:

• GALasm
• galette

It parses pin definitions and logic equations. Assembler directives and declarations not related to logic definition are ignored.

Installation

Requires Python 3.8 or later. No external dependencies.

git clone https://github.com/Ho-Ro/pld2vect.git
cd pld2vect
chmod +x pld2vect.py

Testing the Program

The provided MKTEST.sh creates test vectors for all sample .pld files in the directory PLD and puts the resulting vectors in the directory VECTORS. The sample .pld files are taken from the galette-testcases.

Usage

Generate Test Vectors

python pld2vect.py my_design.pld > test_vectors.xml

my_design.pld is the same file you use with GALasm or galette to assemble your JEDEC.

Verify a Programmed GAL With minipro

# Step 1: Assemble JEDEC with GALasm (as usual)
galasm my_design.pld

# Step 2: Program the GAL
minipro -p GAL16V8 -w my_design.jed

# Step 3: Generate test vectors from the same .pld file
python pld2vect.py my_design.pld > my_design.xml

# Step 4: Verify with minipro
minipro -p GAL16V8 -T --logicic my_design.xml

Input Format

Standard .pld file as used by GALasm/galette:

Expression Syntax

Operator    Meaning Example
*           AND     I0 * I1
+           OR      I2 + I3
/           NOT     /I4
^           XOR     I0 ^ I1 (equivalent to I0 * /I1 + /I0 * I1)

Constants:
VCC — logic 1
GND — logic 0

Input File Examples

Simple Logic Example

GAL16V8
Simple Logic

Clock I0    I1    I2    I3    I4    I5    NC    NC   GND
/OE   O0    O1    O2    O3    O4    NC    NC    NC   VCC

O0 = I0 * I1              ; AND gate
O1 = I2 + I3              ; OR gate
O2 = I4 * /I5 + /I4 * I5  ; XOR gate
/O4 = I0 + I1 + I2 + I3   ; NOR gate (active low)

DESCRIPTION
Simple logic example

Registered Logic Example

GAL22V10
Registered Counter

Clock I0    I1    I2    I3    NC    NC    NC    NC    NC    NC   GND
/OE   O0    O1    O2    NC    NC    NC    NC    NC    NC    NC   VCC

O0.R = /O0                 ; Toggle flip-flop
O1.R = O0 ^ O1             ; Binary counter
O2.R = O0 * O1 ^ O2

DESCRIPTION
Registered logic example

Tristate Example

GAL16V8
Tristate Buffer

Clock I0    I1    I2    I3    I4    I5    NC    NC   GND
NC    O0    O1    O2    O3    O4    NC    NC    NC   VCC

O0.T = I0 * I1             ; Data expression
O0.E = I2                  ; Enable expression (1 = driven, 0 = high-Z)

DESCRIPTION
Tristate example

Per-Output Clock and Async Control

GAL20RA10
Advanced Registered

Clock I0    I1    I2    I3    I4    I5    I6    I7    I8    Clock   GND
/OE   O0    O1    O2    O3    O4    O5    O6    O7    NC    NC      VCC

O0.R = I0 * I1
O0.CLK = Clock

O5.R = I6 + I7
O5.CLK = Clock
O5.ARST = I0               ; Asynchronous reset for this output only
O5.APRST = I1              ; Asynchronous preset for this output only

O6.R = I6
O6.CLK = Clock * O6        ; Gated clock

O7.R = I7
O7.CLK = /Clock            ; Inverted clock

DESCRIPTION
Per-output clock and async control

Output Format

The generated test vectors in XML format:

<?xml version="1.0" encoding="utf-8"?>
<logicic>
  <database type="LOGIC">
    <custom name="CombTest">
      <ic name="GAL16V8" type="5" voltage="5V" pins="20">
        <vector id="00"> 0 0 0 0 0 0 0 X X G 0 L L L L H 0 X X V </vector>
        <vector id="01"> 0 1 0 0 0 0 0 X X G 0 L L L L L 0 X X V </vector>
        <vector id="02"> 0 0 1 0 0 0 0 X X G 0 L L L L L 0 X X V </vector>
        <vector id="03"> 0 0 0 1 0 0 0 X X G 0 L H L L L 0 X X V </vector>
        <vector id="04"> 0 0 0 0 1 0 0 X X G 0 L H L L L 0 X X V </vector>
        <vector id="05"> 0 0 0 0 0 1 0 X X G 0 L L H L L 0 X X V </vector>
        <vector id="06"> 0 0 0 0 0 0 1 X X G 0 L L H L L 0 X X V </vector>
        <vector id="07"> 0 0 0 0 0 0 0 X X G 0 L H L L H 1 X X V </vector>
        <vector id="08"> 0 1 1 1 1 1 1 X X G 0 H H L H L 1 X X V </vector>
        <vector id="09"> 0 0 0 0 0 0 0 X X G 1 Z Z Z Z Z 0 X X V </vector>
      </ic>
    </custom>
  </database>
</logicic>

Vector Format:

0, 1 — input states
L, H — expected output states (low, high)
Z — high impedance (tristate disabled)
X — don't care (NC pin)
G — ground (GND pin)
V — VCC pin

File Structure

pld2vect.py              # Main entry point (CLI)
device_model.py          # Device, Pin, Equation dataclasses
parser.py                # .pld file parser (GALasm/galette compatible)
expression.py            # Boolean expression evaluator
solver.py                # Combinatorial feedback solver
generator.py             # Test vector generator

Limitations

• No sequential depth testing — generates input patterns and simulates state transitions, but does not exhaustively test all possible state sequences for complex state machines.

• Input combinations — exhaustive for ≤6 inputs, walking-ones subset for larger widths (configurable via exhaustive parameter in generate_vectors()).

• Timing — purely functional verification; no timing parameters or propagation delays.

• Output format — may need adaptation for specific minipro versions.

Contributing

Bug reports and feature requests are welcome. Please include a minimal .pld file that reproduces the issue.

License

The tool pld2vect is released under GPL version 3, see LICENSE.
SPDX-License-Identifier: GPL-3.0-or-later

jedutil

I've also added the tool jedutil and its man page jedutil.1.gz from the debian package mame-tools. Among other things, it allows you to dump the logic equations of jedec files:

$ jedutil -h
Usage:
  jedutil -convert <source.jed> <target.bin> [fuses] -- convert JEDEC to binary form
  jedutil -convert <source.pla> <target.bin> [fuses] -- convert Berkeley standard PLA to binary form
  jedutil -convert <source.bin> <target.jed> -- convert binary to JEDEC form
  jedutil -view <source.jed> <device> -- dump JED logic equations
  jedutil -view <source.bin> <device> -- dump binary logic equations
  jedutil -viewlist -- view list of supported devices
  jedutil -listcompatible <source.jed> -- list compatible devices
  jedutil -listcompatible <source.bin> -- list compatible devices

The tool jedutil is released under the BSD-3-Clause license, see BSD-3-Clause_jedutil.txt.