High-speed serial signaling in data center switches — SerDes architecture, line coding, signal integrity, and link training.
- Background: Switch Architecture: Brief overview of control/data plane separation and why NPUs exist — context for understanding where SerDes fits in a switch.
- NPU Silicon: NPU vendor landscape, Broadcom switching ASIC generations (Tomahawk, Trident, Jericho), and software-based forwarding alternatives (VPP/DPDK).
- SerDes and Lanes: How an NPU connects to the outside world — serialization, lane and port architecture, and port breakout.
- Digital Signal Fundamentals: Encoding schemes, signal integrity, eye diagrams, and impairments like ISI and crosstalk at multi-gigabit rates.
- Link Equalization and Training: Pre-emphasis, CTLE, DFE, and the auto-negotiation and training protocols that make links work at 25G+ per lane.