Name		Name	Last commit message	Last commit date
assets		assets
docs		docs
implementation		implementation
rtl		rtl
tb		tb
verification		verification
LICENSE		LICENSE
README.md		README.md

Repository files navigation

⏰ Digital Alarm Clock (Verilog HDL)

Overview

🏗️ Project Architecture

Features

Architecture

FSM Design

Project Structure

Simulation

RTL Synthesis

Results

Tools Used

Future Improvements

Author

About

Digital Alarm Clock in Verilog HDL | FSM | ModelSim | Intel Quartus Prime | FPGA RTL Design

alarm-clock alarm-clock-project digital-design digital-design-verification fpga fsm fsm-controller fsm-design modelsim quartus-prime rtl rtl-design-and-verification systemverilog verilog vlsi vlsi-design vlsi-project

1 star

1 watching

Report repository

Releases

Packages

Contributors

Languages