Modeling and Simulation of Dual Material Gate Junctionless FinFET using Synopsys Sentaurus TCAD.
This repository contains the Synopsys Sentaurus TCAD project files, scripts, and simulation setup for modeling a Dual Material Gate Junctionless FinFET (DMG-JLFET) with gate length of 10nm. The work includes structure creation in Sentaurus Structure Editor, implementation of suitable physical models in the device simulation (sdevice) script, and automation of performance metric extraction (Threshold Voltage, Leakage Current, DIBL, Subthreshold Slope) using svisual scripting.
- Sentaurus Structure Editor (sde) – for device geometry and mesh generation.
- Sentaurus Device (sdevice) – for electrical simulation with appropriate physics models.
- Sentaurus Visual (svisual) – for post-processing and pLot visualization.
- Shell / TCL scripting – for automation.