CMOS Half Adder design using Cadence Virtuoso including schematic design, simulation and layout verification (DRC, LVS REX).
This project demonstrates the design and verification of a CMOS Half Adder using Cadence Virtuoso. The Half Adder is a fundamental combinational circuit used to perform binary addition of two input bits.
The project follows the standard VLSI design methodology including schematic design, symbol generation, functional simulation, layout design, physical verification, and parasitic RC extraction.
Technology : CMOS Design Tool : Cadence Virtuoso Simulator : Spectre Verification : DRC, LVS Extraction : RC Parasitic Extraction
A Half Adder is a combinational logic circuit that adds two single-bit binary numbers and produces two outputs:
• Sum (S) • Carry (C)
The Sum output represents the result of the binary addition, while the Carry output indicates overflow from the addition.
Sum Output
S = A ⊕ B
Carry Output
C = A · B
| A | B | Sum | Carry |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
The Sum output behaves as an XOR operation while the Carry output behaves as an AND operation.
- Logic Design
- Transistor Level Schematic
- Symbol Creation
- Testbench Design
- Functional Simulation
- Layout Implementation
- Design Rule Check (DRC)
- Layout Versus Schematic (LVS)
- RC Parasitic Extraction
The schematic was implemented in Cadence Virtuoso using CMOS transistors to realize the Half Adder logic.
A symbol view was generated so that the Half Adder can be reused in hierarchical circuit designs.
A testbench circuit was created to apply input signals and verify the functionality of the Half Adder.
Transient simulation confirms correct behavior of Sum and Carry outputs.
The physical layout was implemented following CMOS layout design rules including proper device placement and routing.
DRC verification confirms that the layout follows fabrication constraints.
LVS ensures that the layout connectivity matches the schematic netlist.
The LVS match confirms that the schematic and layout are electrically identical.
Parasitic extraction identifies resistance and capacitance introduced by layout interconnects.
The RC network represents parasitic elements used for accurate post-layout simulation.
• Correct Half Adder functionality verified • DRC passed successfully • LVS matched successfully • RC parasitic extraction completed
Cadence Virtuoso Spectre Simulator Assura / Calibre
Abhijit Wankhede