- π± Deepening my expertise in Computer Architecture, Machine Learning, and Cyber Security
- π§ Strong foundation in C/C++, VHDL, and Python
- π§ Interested in digital IC design & acceleration: algorithm mapping β microarchitecture design β RTL synthesis β FPGA validation
- β‘ Learning by building β improving one commit at a time
- π« Reach me at:
bryan.herdianto17@gmail.com
Pinned Loading
-
sar-pam-balancing-robot
sar-pam-balancing-robot PublicSaR-PaM is an ESP32-based self-balancing two-wheel robot using an MPU6050 and PID control, built on a dual-core FreeRTOS architecture for stable real-time balancing. It features command-based path β¦
C++ 1
-
diabetes-detection-mlops
diabetes-detection-mlops PublicAutomated MLOps pipeline for diabetes detection using TFX, GitHub Actions, and Render.
Jupyter Notebook
-
oprec-digilab
oprec-digilab PublicModern NextJS recruitment platform using Supabase for authentication, storage, and database management.
TypeScript 1
-
16bit-risc-cpu
16bit-risc-cpu PublicSynthesizable 16-bit RISC CPU core designed in VHDL with an 8-bit ALU, 16 general-purpose registers, an 8-state FSM, and full ModelSim testbench coverage.
VHDL
-
image-convolution
image-convolution PublicA modular VHDL image convolution system with ALU (direct) and MMU (im2col) processing units supporting multiple kernels.
VHDL
-
l1-cache-controller
l1-cache-controller PublicParameterized 2-Way Set-Associative L1 Cache Controller written in Verilog with 1-cycle hits, write-back dirty handling, and automated ModelSim testbench.
Verilog
If the problem persists, check the GitHub status page or contact support.



