Skip to content
View bryanherdianto's full-sized avatar

Organizations

@Gladiatos-Programming @brain-ui @4E-org

Block or report bryanherdianto

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
bryanherdianto/README.md

Hi, I'm Bryan πŸ‘‹

Aspiring Engineer

πŸ‘¨β€πŸ’» About Me

  • 🌱 Deepening my expertise in Computer Architecture, Machine Learning, and Cyber Security
  • 🧠 Strong foundation in C/C++, VHDL, and Python
  • πŸ”§ Interested in digital IC design & acceleration: algorithm mapping β†’ microarchitecture design β†’ RTL synthesis β†’ FPGA validation
  • ⚑ Learning by building β€” improving one commit at a time
  • πŸ“« Reach me at: bryan.herdianto17@gmail.com

Pinned Loading

  1. sar-pam-balancing-robot sar-pam-balancing-robot Public

    SaR-PaM is an ESP32-based self-balancing two-wheel robot using an MPU6050 and PID control, built on a dual-core FreeRTOS architecture for stable real-time balancing. It features command-based path …

    C++ 1

  2. diabetes-detection-mlops diabetes-detection-mlops Public

    Automated MLOps pipeline for diabetes detection using TFX, GitHub Actions, and Render.

    Jupyter Notebook

  3. oprec-digilab oprec-digilab Public

    Modern NextJS recruitment platform using Supabase for authentication, storage, and database management.

    TypeScript 1

  4. 16bit-risc-cpu 16bit-risc-cpu Public

    Synthesizable 16-bit RISC CPU core designed in VHDL with an 8-bit ALU, 16 general-purpose registers, an 8-state FSM, and full ModelSim testbench coverage.

    VHDL

  5. image-convolution image-convolution Public

    A modular VHDL image convolution system with ALU (direct) and MMU (im2col) processing units supporting multiple kernels.

    VHDL

  6. l1-cache-controller l1-cache-controller Public

    Parameterized 2-Way Set-Associative L1 Cache Controller written in Verilog with 1-cycle hits, write-back dirty handling, and automated ModelSim testbench.

    Verilog