cranelift: fix missing ISLE lowering rules from #12197 on AArch64, x86_64, and RISC-V

[dsecurity49]

Resolves missing ISLE rules from #12197 on AArch64, x86_64, and RISC-V.

1. AArch64:

   • vhigh_bits: Switched vhigh_bits rules from $I* to multi_lane to support float vector types (f32x4, f64x2, f16x8), matching x64 and s390x.
   • band + bnot: Added lowering rules for band(bnot) on scalar floats (f32, f64) to emit a single bic instruction instead of separate mvn + and.

2. x86_64:

   • bitcast_gpr_to_xmm: Added 8-bit byte rule to fix compiler panic in scalar_to_vector.i8x16 / vany_true.i8x16 (using PINSRB on SSE4.1, and MOVZBL + PINSRW on baseline SSE2).

3. RISC-V:

   • select_spectre_guard: Added lowering rule for vector types (ty_supported_vec) using vand.vx, vandn.vx, and vor.vv.

Includes precise-output filetests for all three architectures and enables aarch64 in runtests/simd-vhighbits-float.clif.