Build Scala black boxes to match rocket-chip verilog black boxes

[chick]

Rocket supplies the following verilog black boxes. The goal is to implement these in scala so treadle can run more rocket instances
AsyncResetReg.v
ClockDivider2.v
ClockDivider3.v
EICG_wrapper.v
SimDTM.v
SimJTAG.v
TestDriver.v
plusarg_reader.v

[ducky64]

Alternatively, can some of those be replaced with Chisel modules since we now have support for async reset reg?

[chick]

I think they can but the goal here is to make it possible to run some existing rocket designs without having to change code (or change it too much)