AES Side-Channel Key Recovery & GF(16) Hardware Arithmetic

Academic Affiliation: Course Project for CS 6102: Implementation Security in Cryptography, IIT Bombay
Instructor: Prof. Sayandeep Saha

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📌 Executive Summary

This repository contains cryptographic hardware implementations and side-channel power analysis pipelines for the Advanced Encryption Standard (AES).

The project spans two core domains:

1. Finite-Field Arithmetic ($GF(2^4)$): Behavioral and synthesizable Verilog HDL modules alongside cycle-accurate C++ benchmarks evaluating Galois field multiplier latency and the AES key schedule (expandSK).
2. Side-Channel Cryptanalysis: Recovery of the full 128-bit AES secret key from real electromagnetic and power consumption traces using Correlation Power Analysis (CPA) and multivariate Gaussian Template Attacks.

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🔬 Core Components

Part 1: $GF(16)$ Multiplier & AES Key Schedule (CS6102_assignment-1/)

• Verilog Hardware Design: Pure combinational and registered Galois field multiplier modules over $GF(2^4)$ defined by irreducible polynomials. Verified with comprehensive testbenches.
• C++ Benchmarking: Software implementation utilizing bitwise XOR polynomial division, benchmarked against cycle-optimized lookup baselines.
• Key Schedule (expandSK): Full implementation of the AES round-key expansion pipeline leveraging the finite-field arithmetic primitives.

Part 2: Power Analysis & Template Attacks (CS6102_assignment-2/)

• Leakage Model: Exploits data-dependent power leakage occurring during the first AES round $S\text{-box}$ lookup: $Z = \text{SBox}(P \oplus K)$.
• Multivariate Gaussian Modeling: Estimates probability density from profiled training traces.
• Maximum Likelihood Key Extraction: Ranks log-likelihood scores across attack traces to reliably extract every byte of the cryptographic key.

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📁 Repository Structure

├── CS6102_assignment-1/         # Finite-field multiplier & expandSK
│   ├── part1/                   # Verilog HDL implementation and testbenches
│   ├── part2/                   # C++ cycle-benchmarked software implementations
│   └── part3/                   # expandSK algorithm
└── CS6102_assignment-2/         # Side-channel cryptanalysis
    ├── template_attack.py       # Multivariate Gaussian template attack engine
    ├── template_attack_2.py     # Refined POI SNR extractor
    ├── template_attack_3.py     # Full 16-byte key extraction verification
    └── attack_traces_team_7.npz # Power trace dataset

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🚀 Getting Started

1. Hardware Multiplier Simulation (Verilog)

cd CS6102_assignment-1/part1
iverilog -o sim_tb tb_multiplier.v multiplier.v
vvp sim_tb

2. Software Arithmetic Benchmark (C++)

cd ../part2
g++ -std=c++17 -O3 -o bench main.cpp
./bench

3. Run Side-Channel Key Recovery

cd ../../CS6102_assignment-2
pip install numpy scipy matplotlib

python3 template_attack.py