Low-voltage powertrain firmware and control systems for the DJS Racing electric Formula Bharat car. Developed as Powertrain Low Voltage Head, leading a 6-member sub-team across PCB design, embedded firmware, and field validation (SAE Formula Bharat 2023 — 5th Overall, 2nd in Cost Category).
The car runs a 7S2P accumulator of NMC 21700 lithium-ion cells, with the low-voltage systems responsible for safe energy delivery, throttle control, and the safety interlocks required to pass Formula Bharat technical scrutiny.
- ecu/ — Engine Control Unit firmware (ATmega32A). Ready-to-drive sequence, dual-APPS throttle plausibility, brake-system plausibility (BSPD), and throttle-to-PWM motor control. [code in this repo]
The following subsystems were part of my powertrain role and are documented in the team's design report; their code will be added here as it is cleaned up:
- Data acquisition (DAQ) — ESP32 dual-core telemetry and logging system (SD/USB logging, LoRa + Wi-Fi), built to resolve a long-standing integration gap and improve sensor data reliability during testing.
- Battery Management (BMS) — cell balancing, protection, and the precharge/discharge logic for the 7S2P NMC pack.
- Cell selection study — trade analysis of candidate 21700 cells (energy density, continuous/peak discharge, cost) feeding the accumulator design.
The low-voltage firmware implements the plausibility and shutdown logic mandated by Formula Bharat rules — accelerator/brake plausibility, brake-system plausibility (BSPD), and continuous monitoring of the shutdown circuit — so the tractive system can only stay live when all checks pass.
This is competition firmware developed in 2022–2024, cleaned up and documented here for reference. Code compiles for its target microcontrollers; flashing and running require the team's hardware and an AVR programmer.