Name		Name	Last commit message	Last commit date
BUFG.v		BUFG.v
BUFGCE_DIV.v		BUFGCE_DIV.v
BUFG_GT.v		BUFG_GT.v
CARRY4.v		CARRY4.v
CARRY8.v		CARRY8.v
CFGLUT5.v		CFGLUT5.v
DSP48E2.v		DSP48E2.v
FDCE.v		FDCE.v
FDPE.v		FDPE.v
FDRE.v		FDRE.v
FDSE.v		FDSE.v
FIFO36E2.v		FIFO36E2.v
GND.v		GND.v
IBUFDS.v		IBUFDS.v
IBUFDS_GTE3.v		IBUFDS_GTE3.v
LDCE.v		LDCE.v
LDPE.v		LDPE.v
LICENSE		LICENSE
LUT1.v		LUT1.v
LUT2.v		LUT2.v
LUT3.v		LUT3.v
LUT4.v		LUT4.v
LUT5.v		LUT5.v
LUT5_D.v		LUT5_D.v
LUT5_L.v		LUT5_L.v
LUT6.v		LUT6.v
LUT6_2.v		LUT6_2.v
LUT6_D.v		LUT6_D.v
LUT6_L.v		LUT6_L.v
MUXF7.v		MUXF7.v
MUXF7_D.v		MUXF7_D.v
MUXF7_L.v		MUXF7_L.v
MUXF8.v		MUXF8.v
MUXF8_D.v		MUXF8_D.v
MUXF8_L.v		MUXF8_L.v
MUXF9.v		MUXF9.v
ODDRE1.v		ODDRE1.v
RAM128X1D.v		RAM128X1D.v
RAM128X1S.v		RAM128X1S.v
RAM256X1D.v		RAM256X1D.v
RAM256X1S.v		RAM256X1S.v
RAM32M.v		RAM32M.v
RAM32M16.v		RAM32M16.v
RAM32X1D.v		RAM32X1D.v
RAM32X1S.v		RAM32X1S.v
RAM512X1S.v		RAM512X1S.v
RAM64M.v		RAM64M.v
RAM64M8.v		RAM64M8.v
RAM64X1D.v		RAM64X1D.v
RAM64X1S.v		RAM64X1S.v
RAMB16BWER.v		RAMB16BWER.v
RAMB18E2.v		RAMB18E2.v
RAMB36E2.v		RAMB36E2.v
RAMB8BWER.v		RAMB8BWER.v
README.md		README.md
SRL16E.v		SRL16E.v
SRL32E.v		SRL32E.v
SRLC16E.v		SRLC16E.v
SRLC32E.v		SRLC32E.v
VCC.v		VCC.v

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verilator_xilinx

Re-coded Xilinx primitives for Verilator use

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Re-coded Xilinx primitives for Verilator use

fpga verilator verilog xilinx-fpga

BSD-2-Clause license

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