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[dv,sram] add axi_sram verification plan and tag architecture spec - #667

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tchilikov-semify wants to merge 4 commits into
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[dv,sram] add axi_sram verification plan and tag architecture spec#667
tchilikov-semify wants to merge 4 commits into
lowRISC:mainfrom
tchilikov-semify:axi_vplan

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@tchilikov-semify

@tchilikov-semify tchilikov-semify commented Jul 10, 2026

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This PR adds a verification plan for the axi_sram, and makes some minor updates to the specification. It also tags the specification and adds a markdown memory map table to it.

@martin-velay martin-velay left a comment

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I have some comments, and also I'd like to know if you feel it was a bad experience to create a vPlan based on DVPlan? I think you are among th 1st to do the full exercise (except myself) and I need to get feedback 😃

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Comment thread hw/top_chip/dv/axi_sram/axi_sram_vplan.hjson
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Thanks for the feedback, @martin-velay 😃

Regarding DVPlan: I found that the flow and working with the tool was actually quite nice and polished (so far).
I was very fond of the ability to start with a CSV and convert to an HJSON after the fact.

One pain point I have though, is the spec annotation capabilities. A random generated tag means that each time the spec is updated and changed, all of the tags would be re-generated. This would make updating the vplans a bit of a nightmare, since all of the tags would have to be re-mapped.

I think a solution to this could be a per-line / per-sentence hash. This way, the hash only changes if the contents of the line change.

Of course, this sounds simple but it would introduce edge cases (white spaces, punctuation, etc).

I have yet to re-generate or re-map anything, but I anticipate that this would be tedious as it currently stands.

Other than this, it was quite straight-forward!

I plan to map the actual SV testcases with a comment to the tags as well.

@martin-velay

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Thanks for the feedback, @martin-velay 😃

Regarding DVPlan: I found that the flow and working with the tool was actually quite nice and polished (so far). I was very fond of the ability to start with a CSV and convert to an HJSON after the fact.

One pain point I have though, is the spec annotation capabilities. A random generated tag means that each time the spec is updated and changed, all of the tags would be re-generated. This would make updating the vplans a bit of a nightmare, since all of the tags would have to be re-mapped.

I think a solution to this could be a per-line / per-sentence hash. This way, the hash only changes if the contents of the line change.

Of course, this sounds simple but it would introduce edge cases (white spaces, punctuation, etc).

I have yet to re-generate or re-map anything, but I anticipate that this would be tedious as it currently stands.

Other than this, it was quite straight-forward!

I plan to map the actual SV testcases with a comment to the tags as well.

Thanks @tchilikov-semify for the feedback.
You could try to update the spec locally and run again the tagging script, I think only the new untagged lines will get a new tag, the others should remain the same. But if a given line change its content, the tag won't be updated and it's up to the approvers to flag that the vPlan should be updated. This is maybe flaky and we also were thinking about having short hashes instead. I am unsure if we have an opened issues but I think that's something to explore further.

@marnovandermaas marnovandermaas left a comment

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I've left some reviews on the initial commits (the vplan I'll leave to @martin-velay

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@tchilikov-semify
tchilikov-semify force-pushed the axi_vplan branch 2 times, most recently from e7efcf5 to 4f6c554 Compare August 11, 2026 10:05
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@tchilikov-semify
tchilikov-semify force-pushed the axi_vplan branch 2 times, most recently from 7df23d3 to ccbd09d Compare August 11, 2026 13:22
Comment thread hw/top_chip/dv/axi_sram/axi_sram_vplan.hjson Outdated
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3 participants