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@warclab Warwick Adaptive and Reconfigurable Computing Lab

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    12 repositories

    • edalize

      Public
      An abstraction library for interfacing EDA tools
      Python
      •
      BSD 2-Clause "Simplified" License
      •234•0•0•0•Updated Sep 15, 2021Sep 15, 2021

    • fusesoc

      Public
      Package manager and build abstraction tool for FPGA/ASIC development
      Python
      •
      BSD 2-Clause "Simplified" License
      •280•1•0•0•Updated Sep 15, 2021Sep 15, 2021

    • warc-cores

      Public
      FuseSoC cores
      0•0•0•0•Updated Sep 7, 2021Sep 7, 2021

    • hls-examples

      Public
      WARC lab HLS examples
      C++
      •0•1•0•0•Updated May 16, 2021May 16, 2021

    • xilinx-userspace-dma

      Public
      Forked version of xilinx_dma driver that support kernel v4.19
      C
      •
      MIT License
      •0•3•0•0•Updated Apr 13, 2021Apr 13, 2021

    • ieee-template

      Public template
      LaTeX Template for IEEE Transactions Format
      TeX
      •
      MIT License
      •3•1•0•0•Updated Aug 17, 2020Aug 17, 2020

    • idea

      Public
      iDEA FPGA Soft Processor
      Verilog
      •6•17•2•0•Updated Jun 9, 2016Jun 9, 2016

    • dyract

      Public
      DyRACT Open Source Repository
      Verilog
      •4•16•1•0•Updated May 4, 2016May 4, 2016

    • zycap

      Public
      Zynq PR Management
      VHDL
      •12•13•1•0•Updated Apr 20, 2016Apr 20, 2016

    • bib

      Public
      TeX
      •0•0•0•0•Updated Nov 17, 2014Nov 17, 2014

    • prcontrol

      Public
      Partial Reconfiguration Controller for Xilinx FPGAs
      Verilog
      •9•12•0•0•Updated Sep 13, 2012Sep 13, 2012

    • archntu.github.com

      Public
      Arch at NTU
      0•0•0•0•Updated Aug 13, 2012Aug 13, 2012
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