fix(decoder): SIMD (v128) ops loud-skip — category-level catch, no silent no-op drop (#680)

[avrabe]

Fixes #680.

Problem

On -t cortex-m3 (no SIMD hardware) WASM SIMD (v128) ops silently compiled to zero machine code: i32x4.add returned an operand passthrough (mov r0,r1) and v128.store left memory unwritten — wrong result shipped with rc=0. The #554 class (aarch64 f32 drop), here for v128 on the thumb backend.

Root cause: the decoder decodes a large v128 subset into WasmOp variants, but the only selector arms for them are gated on a has_helium flag nothing in the production pipeline sets (test-only MVE prototype) — so selection dropped them without a diagnostic. The GI-FPU-001 loud-skip (#371) only fires for ops that decode to None; the decoded-but-unselectable v128 ops sailed past it. Per-op-incomplete honesty is exactly how this slipped through (v128.any_true was loud, i32x4.add silent).

Fix — category-level, no wildcard drop survives

• is_simd_operator — macro-generated from wasmparser's own for_each_operator! proposal markers (@simd / @relaxed_simd): covers the entire SIMD operator space of the pinned wasmparser, no hand-kept op list to fall out of date. Any SIMD-proposal operator routes the function through the established machinery: fix(#369): unsupported decoder ops loud-skip, never silently drop (GI-FPU-001) #371 all-exports loud-skip with a named reason, fix(aarch64): reject f32 ops honestly instead of silent miscompile (#554) #556 single-function honest bail.
• v128-typed locals + v128 params/results flag too — expressible with zero SIMD operators (local.get 0 passthrough), lowered as 4-byte moves that silently truncate the 16-byte value. Both decode entry points, following the fix(decoder): float-typed global accesses loud-skip — the last silent float path (GI-FPU-001, #369) #648 float-global precedent.
• v128-typed global accesses (imported + defined, full index space, imports first) flag — same lane as fix(decoder): float-typed global accesses loud-skip — the last silent float path (GI-FPU-001, #369) #648: the v128.const initializer is never captured and an access moves 4 of the 16 bytes.

The diagnostic says "no SIMD lowering for this target" (not "SIMD invalid") — cortex-m55/MVE can legitimately lift this once the Helium lowering is actually wired to a target.

Oracles (red → green)

• Red on main (7a9222d): both issue reproducers compile rc=0 silently (wrong result under QEMU vs wasmtime per thumb-2: SIMD (v128) ops silently dropped to no-ops on cortex-m3 (no SIMD hw) — wrong result / unwritten memory instead of honest rejection (#554 class) #680).
• Green here: rc=1 with skipping function 'f': ... I32x4Splat: no SIMD lowering for this target — the op would be silently dropped to a no-op (WASM SIMD proposal, #680).
• Non-vacuity: scalar functions in the same module still compile (mixed-module verified: vf skipped, sf emitted, ELF produced).
• New decoder tests (red on main): SIMD-op flag on both issue reproducers, v128 local + op-free v128 signature flag, v128 global access flag with imported-index shift — scalar/i32 siblings asserted unflagged in every test.
• Frozen anchors 10/10 byte-identical (frozen_codegen_bytes); workspace 109 test suites green; cargo fmt --check + chunked clippy --all-targets -- -D warnings clean across all crates.

Lineage: #554 (honest rejection over silent miscompile), #665 (intentionally-ignored class), #648 (typed-global/local precedent), #371/#556 (loud-skip / honest-bail machinery), #369 (GI-FPU-001).

🤖 Generated with Claude Code

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Codecov Report

❌ Patch coverage is 96.26168% with 8 lines in your changes missing coverage. Please review.

Files with missing lines	Patch %	Lines
crates/synth-core/src/wasm_decoder.rs	96.26%	8 Missing ⚠️

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