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Add measured converter comparison (AES17 THD+N/DR) and landscape doc - #9
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notebooks/asrc_comparison.ipynb measures SampleRateTap, libsamplerate (sinc_best) and soxr (VHQ) under one identical AES17-style measurement: 997 Hz at -1 dBFS across a +200 ppm crossing, exact-fit fundamental removal + +-20 Hz notch, 20 Hz-20 kHz integration; AES17 DR at -60 dBFS A-weighted. Outputs are additionally quantized to a 24-bit interface, the condition under which software numbers are directly comparable to hardware ASRC datasheets. The instrument is calibrated in-notebook against synthetic signals with known answers (exact to 0.01 dB) and the SampleRateTap results are assertion-pinned. Measured: SampleRateTap -132.1 dB THD+N / 149.1 dB DR at the 24-bit interface with the servo recovering the clock; oracle-fed libraries sit at the format ceilings (-143.5 dB / 149.1 dB); naive FIFO -34.7. Notable methodology trap documented in-notebook: including a one-shot converter's end-of-stream filter flush in the analysis window poisons its measurement by ~60 dB. docs/COMPARISON.md carries the measured table plus the structural landscape (hardware chips with sourced datasheet values, zita, OS engines) and plainly-stated caveats. README links both.
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Answers "how does this compare to other ASRCs?" with measurements instead of quotes, and adds the landscape document.
notebooks/asrc_comparison.ipynb— identical-conditions measurementOne AES17-style measurement implementation applied to every software subject: 997 Hz at −1 dBFS across a +200 ppm clock crossing, fundamental removed by exact LS fit (phase-slope frequency refinement) + ±20 Hz notch, residual integrated 20 Hz–20 kHz; DR per AES17 (−60 dBFS, A-weighted). Every output is also quantized to a 24-bit interface — the equalizer that makes software numbers directly comparable to hardware datasheets, since that's what silicon presents at its pins. The instrument self-calibrates against synthetic signals (exact to 0.01 dB) before measuring anything.
sinc_bestVHQContext: the oracle libraries measure at the format ceilings (near-unity is their easy regime); SampleRateTap's number includes clock recovery and causal 1.5 ms-latency operation — the ~11 dB gap is the measured price of the half of the problem the libraries don't solve. Against silicon: −132 dB sits at the AD1896's "best" datasheet figure (−133) with DR above both chips' 142/144 dB (pristine digital vs analog bench — caveated in the docs).
Two methodology findings baked into the notebook so they aren't retraced: a one-shot converter's end-of-stream filter flush poisons a tail-anchored analysis window by ~60 dB (caught via a 2:1 control experiment), and float-native AES17 DR mostly measures the arithmetic format (192–212 dB!) — hence the 24-bit interface convention.
docs/COMPARISON.mdThe measured table plus the structural landscape: AD1896 / SRC4392 with sourced datasheet values, libsamplerate/soxr/zita/OS engines, columns for clock recovery, ratio range, latency, footprint, license — and a caveats section that states plainly what is and isn't comparable. README links both from the Measured performance section.
https://claude.ai/code/session_01HuAFfoeD5a5Xe5aGNA16M9
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