analog-ic-design

Common-Centroid Placement Algorithm for IC design elements

Generate folded-cascode opamp parameters with interactive CLI.

Deadlines for Conferences which are relevant to the research topics of E&D

Reference voltage: 315 mV Supply range: 1.0 V -3.3 V Temperature coefficient: ≈ 15 ppm/°C (−40 °C to 125 °C)

Design and simulation of a two-stage CMOS OpAmp in Cadence Virtuoso. Verified via PVT corners and Monte Carlo analysis.

This repository contains all the designs done by Shreyas Singh in the VLSI related Labs-Digital VLSI design(5th semester) and Current Mode Analog VLSI desig(6th sem)

Documentation and performance reports for an ultra-low-power dual-loop LDO of PMIC designed during my internship.

A 2.7μW, 127dB CMRR 3-OpAmp Instrumentation Amplifier with Driven-Right-Leg feedback for wearable biopotential monitoring in 180nm CMOS.

Design, simulation and full verification of a CMOS transimpedance amplifier.

MY JOURNEY TO BE AN ANALOG IC ENGINEER . Self-learning projects using industry standard EDA tools. [Work-In-Progress]

Comparative study and design analysis of current mirror topologies in analog IC design.

# Low Noise Low Power Two-Stage CMOS Operational Amplifier. A transistor-level CMOS operational amplifier designed in Cadence Virtuoso using the GPDK180 technology. The design targets audio signal processing applications requiring low noise, high gain and low power consumption.

CMOS PWM Generator designed and simulated in LTspice. The project demonstrates pulse-width modulation using a behavioral ramp source, transistor-level CMOS comparator, and CMOS output logic operating from a 1.8 V supply. It serves as an early-stage mixed-signal IC design prototype.

Transistor-level design of a low-power (1.18mW) Two-Stage Folded-Cascode OTA in 0.18µm CMOS. Optimized for high DC gain and bandwidth utilizing the systematic gm/ID sizing methodology.

Engineering traceability framework for Cadence Virtuoso ADE XL using SKILL and Python.

Neural Network models for automating design parameters of CS amplifier. Includes automated SPICE data generation and model validation in Python and MATLAB.

Transistor-level LTspice study of a standard 6T SRAM cell, Single Event Upset fault injection, and a radiation-hardened DICE memory cell for space electronics applications.

Design and simulation of a low-power Bulk-Driven OTA using the DI-Tram (Degenerative Current Translation and Mirroring) architecture in Cadence Virtuoso with UMC 180 nm CMOS technology.

1.2 V two-stage Miller OTA in 90 nm CMOS — 67 dB, 49 MHz, 279 µW. Hand-derived compensation, 12-corner PVT, 500-point Monte Carlo.

Investigation of CMOS bandgap reference operating principles using LTspice simulations. The project demonstrates CTAT and PTAT voltage generation, PTAT current generation, and temperature compensation techniques used in analog integrated circuit design..