#
asynchronous-fifo
Here are 20 public repositories matching this topic...
Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
counter fsm asynchronous verilog fifo testbenches verilog-hdl verilog-programs mealy-machine-code moore-machine-code verilog-project fifo-buffer verilog-code n-bit-alu verilogvalidation design-under-test asynchronous-fifo fifo-verilog
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May 10, 2019 - Verilog
An FPGA implementation of Cummings' Asynchronous FIFO
fpga rtl verilog xilinx synthesis systemverilog fifo uvm xilinx-fpga xilinx-vivado digilent hardware-description-language nexys4ddr universal-verification-methodology fpga-programming digilent-nexys-4-board synthesizable asynchronous-fifo uvm-verification register-transistor-level
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Apr 14, 2022 - SystemVerilog
This repository contains an asynchronous FIFO design and a comprehensive UVM testbench for its functional verification. It demonstrates a robust, real-world approach to digital design and verification.
asynchronous-fifo uvm-verification asynchronous-fifo-design-verification asynchronous-fifo-uvm-based-design-verification
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Sep 22, 2025 - SystemVerilog
Parameterized Asynchronous FIFO RTL design with dual-clock domains, Gray-code pointers, CDC synchronizers, and full/empty flag generation.
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Sep 15, 2026
Asynchronous FIFO with CDC Reliability Analyzer built from scratch in Verilog. Gray-code pointers, 2-FF synchronizers, randomized stress testbench, timing closure on Artix-7 (WNS = +6.31 ns). No IP cores used.
fpga verilog hardware-designs cdc vlsi digital-design xilinx-vivado metastability clock-domain-crossing artix-7 asynchronous-fifo rtl-design
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Apr 24, 2026 - Verilog
Parameterized Synchronous and Asynchronous FIFO implementations in Verilog HDL with Gray-code pointer synchronization, CDC handling, and Vivado verification.
verilog fifo cdc vlsi verilog-hdl digital-design xilinx-vivado gray-code clock-domain-crossing asynchronous-fifo rtl-design synchronous-fifo
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Jul 29, 2026 - Verilog
Gray-pointer asynchronous FIFO with two-flop synchronisers, verified against unrelated clocks and a behavioural metastability model that the binary-pointer version fails.
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Aug 26, 2026 - Python
This repository features an asynchronous FIFO design I built from scratch in SystemVerilog. I include RTL designs, thorough test benching, and documentation.
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Aug 5, 2026 - SystemVerilog
Modular Verilog RTL implementation of an asynchronous FIFO with Gray-code pointer synchronization, clock-domain crossing, and Vivado-based verification.
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Sep 24, 2026 - Verilog
Parameterized asynchronous FIFO in Verilog using Gray-coded pointers and 2-stage synchronizers for reliable clock domain crossing, with Full, Empty, Almost-Full and Almost-Empty flags.
verilog vivado fifo cdc vlsi digital-design metastability clock-domain-crossing vlsi-design vlsi-project asynchronous-fifo synchronizers grey-code almost-full almost-empty fifo-asynchronous
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May 8, 2026 - Verilog
A parameterizable Asynchronous FIFO designed in Verilog.
verilog fifo verilog-programs verilog-project verilog-code asynchronous-fifo asynchronous-fifo-design-verification
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Aug 12, 2026 - Verilog
A highly parameterized, synthesizable Asynchronous FIFO designed to safely transfer data between two independent, asynchronous clock domains. This project demonstrates core VLSI concepts including metastability prevention, Gray code synchronization, and static timing closure on an FPGA architecture.
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May 24, 2026 - Verilog
AXI4-Lite slave with a Gray-coded clock-domain-crossing FIFO, verified to 100% functional coverage with a layered SystemVerilog testbench, a UVM environment, and bound SVA properties.
verilog systemverilog uvm sva clock-domain-crossing axi4-lite asic-design asynchronous-fifo functional-coverage rtl-verification
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Sep 2, 2026 - SystemVerilog
Parameterizable Asynchronous FIFO with Gray Code Synchronization - A robust clock domain crossing solution in SystemVerilog
asic fpga verilog systemverilog fifo digital-design gray-code clock-domain-crossing asynchronous-fifo rtl-design
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Nov 20, 2025 - SystemVerilog
Phase-2 Cycle-2: Memory & Architecture Foundations
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Jul 26, 2026 - Verilog
UVM verification of a 64-entry async FIFO across 80/50 MHz clocks: fixed CDC synchronizer reset domains, scoreboard catches injected data corruption, directed flag-threshold tests.
rtl systemverilog cdc uvm gray-code clock-domain-crossing questa hardware-verification design-verification asynchronous-fifo functional-coverage
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Sep 24, 2026 - SystemVerilog
A configurable synchronous and asynchronous FIFO with Gray-code clock-domain crossing, verified with an unbounded SymbiYosys formal proof and self-checking testbenches.
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Sep 1, 2026 - SystemVerilog
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