design-for-manufacturability

Here are 4 public repositories matching this topic...

nknkk6-oss / DesignForManufacturabilityAssembly-DFMA-

DFMA checklist for cold chain | critical spares & food products | reliability, safety, cost-efficient design

packaging logistics refrigeration spare-parts food-safety dfma cold-chain frozenfood design-for-manufacturability design-for-assembly

Updated Aug 20, 2025

933yee / NTHU_VLSI_Design_for_Manufacturability

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VLSI DFM coursework and a C++ power-staple insertion project based on triple-row dynamic programming.

cpp eda dynamic-programming vlsi design-for-manufacturability

Updated Aug 17, 2026
C++

Rakesh-2306 / Performance-Balanced-Noise-Canceling-Low-Noise-Amplifier

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Designed and implemented a performance-balanced noise-canceling LNA in SCL 180nm CMOS using Cadence Virtuoso, covering CG-CS, Cascode, and Folded-Cascode architectures, RF analysis, full-custom layout, DRC/LVS, PEX, and a custom spiral inductor.

calibre cadence-virtuoso mixed-signal rf-analysis linearity noise-cancellation stability-analysis low-noise-amplifier lna noise-analysis cadence-spectre s-parameter design-rule-check design-for-manufacturability scl180nm full-custom-layout parasitic-extraction layout-vs-schematic custom-spiral-inductor

Updated Apr 14, 2026

Rakesh-2306 / Semionics-Analog-Layout-Internship-Training

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Hands-on Analog Layout Internship/Training at Semionics using Cadence Virtuoso and GlobalFoundries 40nm, covering custom analog, mixed-signal, and CMOS circuit layout.

layout calibre cadence-virtuoso digital-design custom-layout cmos-circuits analog-layout layout-design standard-cells custom-analog mixed-signals-design globalfoundries design-rule-check design-for-manufacturability parasitic-extraction layout-vs-schematic gf40nm

Updated Aug 19, 2026

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