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fusesoc

Here are 50 public repositories matching this topic...

chipsalliance / Cores-VeeR-EH1

VeeR EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer

Updated Jul 16, 2026
SystemVerilog

chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core

fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2

Updated Aug 28, 2026
SystemVerilog

chipsalliance / VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2

tools fusesoc swerv veer

Updated Dec 11, 2024
Verilog

m-kru / fsva

FuseSoc Verification Automation

fpga hdl fusesoc

Updated Jul 21, 2022
VHDL

sifferman / fusesoc_template

Example of how to get started with olofk/fusesoc.

vivado icestorm icarus-verilog yosys fusesoc tinyfpga-bx nexys-a7 nextpnr-ice40

Updated Jul 25, 2021
Python

sifferman / fpga_screensaver

This project implements the VGA protocol and allows custom images to be displayed to the screen using the Sipeed Tang Nano FPGA dev board.

fpga fusesoc

Updated Aug 24, 2023
SystemVerilog

ucsbieee / mapache64

Custom 6502 Video Game Console

fpga verilog 65c02 fusesoc cc65 ben-eater-6502 cmod-a7

Updated May 8, 2026
SystemVerilog

dpretet / meduram

Multi-port BRAM IP for ASIC and FPGA

block asic fpga ram yosys iverilog fusesoc bram amba axi4 axi4-lite multi-port svut axi4-lite-interface

Updated Apr 21, 2021
SystemVerilog

sifferman / tangnano_example

Simple example of how to get started with the Tang Nano with FuseSoC.

fusesoc apicula tangnano

Updated Mar 14, 2022
Makefile

midisenpai / rtl-core-library

A set of common RTL cores that I've developed over time and organized into a FuseSoC library.

vhdl rtl verilog systemverilog hdl fusesoc

Updated Jul 19, 2026

midisenpai / spi-bfm

A quick SPI BFM to assist in SPI device testing and development

spi systemverilog fusesoc bfm

Updated May 19, 2026
SystemVerilog

librecores / docker-tools

Just a set of Dockerfiles and tools for FuseSoC

docker verilog icarus-verilog fusesoc

Updated Nov 12, 2018
Dockerfile

ucsbieee / arcade

6502 Arcade Machine by UCSB IEEE

fpga assembly verilog 65c02 fusesoc ben-eater-6502 cmod-a7

Updated Feb 13, 2022
JavaScript

sifferman / fusesoc_project_template

A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.

vscode verilog systemverilog icarus-verilog yosys fusesoc verilator

Updated Aug 2, 2023
Makefile

midisenpai / i2c-bfm

A simple I2C BFM

i2c systemverilog fusesoc bfm

Updated Jul 12, 2026
SystemVerilog

midisenpai / SHA-Module

A simple SHA-256 implementation in VHDL and Verilog, simulated using a basic UVM testbench.

vhdl verilog systemverilog uvm fusesoc

Updated Aug 29, 2026
Verilog

midisenpai / uart-bfm

A simple UART BFM

uart systemverilog fusesoc bfm

Updated Aug 29, 2026
SystemVerilog

find_first_set

sifferman / find_first_set

Find first set operation in Verilog-2001 with logarithmic complexity.

verilog fusesoc find-first-set

Updated Nov 1, 2021
Verilog

euripedesrocha / tbpp

A simple test library for verilator

cpp verilog fusesoc verilator

Updated May 3, 2020
C++

Illusion-Graphics / RISC-16

16-bit RISC core

core systemverilog fusesoc

Updated Jun 28, 2020
SystemVerilog

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