#

gtkwave

Here are 216 public repositories matching this topic...

buserror / simavr

simavr is a lean, mean and hackable AVR simulator for linux & OSX

c debugger embedded avr-gcc gtkwave simavr avr-simulator

Updated Sep 10, 2026
C

HaDes-V

tscheipel / HaDes-V

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design

Updated Feb 2, 2026
SystemVerilog

vcd

yne / vcd

VCD file (Value Change Dump) command line viewer

cli vhdl gtkwave vcd

Updated Nov 9, 2025
C

dpretet / svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

python flow simulator tdd simulation foss verilog testcase tdd-utilities mit-license systemverilog icarus-verilog gtkwave verification-methodologies vcd verilator surfer svut

Updated Oct 22, 2024
Python

IBM / hdl-tools

Facilitates building open source tools for working with hardware description languages (HDLs)

rtl verilog gtkwave hdl verilator

Updated Dec 4, 2019
Perl

JeffDeCola / my-verilog-examples

A place to keep my synthesizable verilog examples.

simulator asic fpga hardware waveform verilog xilinx synthesis vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

Updated May 19, 2026
Verilog

ghdl / docker

Scripts to build and use docker images including GHDL

dockerfiles hardware ci simulation vhdl actions verilog synthesis icestorm gtkwave ghdl testbench vunit yosys openocd pnr nextpnr prjtrellis

Updated Nov 20, 2024
Shell

bodsvei / 2D-systolic-array

A parameterizable Weight-Stationary 2D Systolic Array implemented in Verilog for hardware-accelerated matrix multiplication

google rtl verilog hardware-designs gtkwave vlsi tpu vlsi-design tpu-acceleration chipdesign sillicon systolic-array 2d-systolic-array

Updated Jul 13, 2026
Makefile

albertxie / iverilog-tutorial

Quickstart guide on Icarus Verilog.

verilog signal icarus-verilog gtkwave csc258

Updated Jun 18, 2020
Verilog

Varunkumar0610 / RISC-V-32I-5-stage-Pipeline-Core

Implementation of 5 Stage 32I RISC V Pipeline Processor.

pipeline visual-studio-code riscv verilog icarus-verilog gtkwave

Updated Sep 6, 2024
Verilog

maazm007 / vsdsquadron-mini-internship

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

gcc-complier gtkwave verilog-hdl yosys risc-v iverilog objdump vlsi-design

Updated Jul 21, 2025
C

arhamhashmi01 / rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

vhdl verilog microprocessor vivado hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator rv32im asic-design chip-design 5-stage-pipelined-processor rv32i-processor

Updated Feb 19, 2025
Verilog

dominiksalvet / super-riscv

Superscalar dual-issue RISC-V processor

open-source pipeline core rtl forwarding systemverilog gtkwave testbench superscalar in-order risc-v microarchitecture low-power verilator ahb3-lite instruction-level-parallelism dual-issue riscv-gcc

Updated Aug 4, 2026
SystemVerilog

Alfredosavi / tangnano-hello

Sipeed Tang Nano: Fully Opensource Toolchain for FPGA Synthesis, Place & Route, Simulation and Download/Flash.

Updated Jul 26, 2024
Makefile

machitgarha / parvaj

Easy and fast VHDL simulation tool, integrating GHDL and GTKWave

build simulation test vhdl console-application automated gtkwave ghdl

Updated Jun 16, 2024
PHP

Elphel / vdt-plugin

mirror of https://git.elphel.com/Elphel/vdt-plugin

eclipse ide eclipse-plugin verilog vivado icarus-verilog gtkwave quartus cocotb

Updated Nov 29, 2017
Java

umarcor / SIEAV

Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

matlab octave gtkwave ghdl vunit cosim co-simulation

Updated Sep 10, 2026
VHDL

ShekharShwetank / RISC-V_RTL2GDSII

Learning Path: RISC-V System-on-Chip (SoC) design, from Register Transfer Level (RTL) to a GDSII layout | Complete VLSI design flow using open-source EDA tools.

opensource magic asic rtl icarus-verilog gtkwave yosys risc-v klayout ngspice vlsi-design asic-design openlane gdsii-flow system-on-chip-design

Updated Nov 25, 2025
Verilog

five-embeddev / riscv-gtkwave

GTKWave Decoders for RISCV

gtkwave risc-v vcd objdump elf-parser dissassembler cosimulation

Updated Aug 16, 2025
C++

cclienti / wavedisp

Python classes to create agnostic wave files for HDL simulator viewer

python vhdl verilog gtkwave modelsim vcd surfer rivierapro

Updated Aug 5, 2026
Python

Add this topic to your repo

To associate your repository with the gtkwave topic, visit your repo's landing page and select "manage topics."