🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
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Updated
Jun 22, 2026 - VHDL
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
Repository to store all design and testbench files for Senior Design
Parameterized Ring Oscillator and Testbench. The design is written in Verilog and testbench is developed in SystemVerilog.
Ring oscillator and its application as Physical Unclonable Function (PUF) for password management
Implementation of a Ring Oscillator-based Physically Unclonable Function (PUF) in Sky130, with 8 bits of Challenge-Response Pairs (CRP)
This project implements a tetrahedral oscillator inspired by the paper “Analysis and Design of a Tetrahedral Oscillator” by Richelle L. Smith and Thomas H. Lee. The oscillator is built from coupled inverter pairs, and its operating frequency is tuned by adding capacitive loads to the internal nodes.
All the source files related to the design and simulation of a Ring Oscillator and a Programmable Logic Device(PLD) using the LTSpice XVII simulator for UOM's EN2110 - Electronics - III Module ❄
FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)
The fabricated CORDIC-1, rebuilt on a standard-cell library I designed myself: device physics, transistor sizing, cell layouts and ngspice-to-Liberty characterization all mine. Same RTL bit for bit, so the shuttle chip is the control group. On-die ring oscillators report my own cells' propagation delay in real silicon. Sky130 / TinyTapeout.
Ring oscillator subcircuits
Voltage Controlled Oscillator that produces 1GHz output frequency at voltage 3.3V using IHP PDK as a part of eSim Marathon
Ring-oscillator PLL IP for IHP SG13CMOS5L (SG13G2) — Chipalooza Challenge
90 nm positive-feedback OTA ring-VCO research with architecture screening, practical current mirrors and tuning-range analysis.
Cadence Virtuoso project of 5-stage ring oscillator
Study of deep correlations in (pseudo) random bits.
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