GitHub - underthenightsky/RISC: Single Cycle Processor based on RISC -V Architecture · GitHub

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
.vscode		.vscode
.gitattributes		.gitattributes
ALU.v		ALU.v
ALU_Decoder.v		ALU_Decoder.v
Control_Unit_Top.v		Control_Unit_Top.v
Data_Mem.v		Data_Mem.v
Instruction_Memory.v		Instruction_Memory.v
MUX.v		MUX.v
PC.v		PC.v
PC_Adder.v		PC_Adder.v
Register_File.v		Register_File.v
Sign_Extend.v		Sign_Extend.v
Single_Cycle_Top.v		Single_Cycle_Top.v
Single_Cycle_Top_Tb.v		Single_Cycle_Top_Tb.v
main_decoder.v		main_decoder.v

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Single Cycle Processor based on RISC -V Architecture

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