NE555 explain

astable configuration

NE555 History

source history here (https://www.circuitstoday.com/the-history-555-timer-ic)

History and Overview of the 555 Timer IC

The 555 Timer IC is one of the most renowned and widely used integrated circuits in electronics. However, its fascinating history is often unknown to many. This section walks through the journey of the 555 Timer IC — from its creation to its status today.

Origins and Invention

The 555 Timer IC was invented in 1971 by Hans R. Camenzind, an engineer working at Signetics Corporation (USA). His work on the 555 timer remains one of the most significant contributions in the field of analog IC design.

• The initial design, created in the summer of 1971, used a constant current source and had 9 pins.
• After the first design review, Hans improved it by replacing the current source with a resistor, which:
  • Reduced the pin count from 9 to 8
  • Allowed the IC to fit into an 8-pin DIP package instead of the standard 14-pin package.
• The updated design passed final review in October 1971.

Design Details

• The 555 timer IC contains:
  • 25 transistors
  • 2 diodes
  • 15 resistors
• External components R (resistor) and C (capacitor) are used to define timing intervals.
• The IC was released in 1972 by Signetics as:
  • SE/NE555
  • Packaged in 8-pin DIP and 8-pin TO-5 metal can formats.

Its low cost, versatility, and reliability quickly made it a favorite among engineers and hobbyists. Over time, it was manufactured by over 12 different companies, becoming the best-selling timer IC in the world.

💡 Trivia:
While many believe the name "555" comes from the three internal 5kΩ resistors, Hans Camenzind clarified in his book Designing Analog Chips that the name was actually inspired by Art Fury, a Signetics manager with a fondness for the number 555.

What is a 555 Timer IC?

The 555 Timer IC is a general-purpose integrated circuit used in:

• Timing applications
• Oscillators
• Pulse generation circuits

It is a monolithic timing circuit, providing a stable, reliable, and inexpensive solution for many analog circuit applications. Its most notable features include:

• Generation of precise time delays
• Production of square waveforms with duty cycles from 50% to 100%
• Operation in multiple modes:
  • Monostable (one-shot)
  • Astable (oscillator)
  • Bistable (flip-flop)

The 555 timer remains a cornerstone of analog electronics and is widely used in both educational and professional circuit designs.

NE555 description

Pin diagram

555 Timer Overview

The 555 timer is a precision timing device capable of generating accurate time delays and oscillation. It operates in two primary modes:

Monostable (One-Shot) Mode

In monostable mode, the 555 produces a single output pulse in response to a trigger input. The duration of the pulse is determined by an external resistor and capacitor (RC) network. This mode is typically used for time delay applications.

Astable (Oscillator) Mode

In astable mode, the 555 functions as an oscillator, continuously switching between high and low output states. The output frequency and duty cycle are controlled using two external resistors and one capacitor. This makes the 555 ideal for generating square waves, clock signals, or LED flashers.

Internal Thresholds and Control

• Threshold level: Two-thirds of the supply voltage (2/3 * VCC)
• Trigger level: One-third of the supply voltage (1/3 * VCC)
• These levels can be modified using the control voltage pin.

Functional Behavior

• When the trigger input drops below 1/3 of VCC, the internal flip-flop is set, and the output goes high.
• When the threshold input exceeds 2/3 of VCC, the flip-flop is reset, and the output goes low.
• The RESET pin overrides all other inputs. Pulling RESET low forces the output low and restarts the timing cycle.

Discharge and Output Capabilities

• When the output is low, the discharge pin (DISCH) connects to ground, allowing the timing capacitor to discharge.
• The output can source or sink up to 200 mA, making it suitable for driving TTL inputs, LEDs, or relays.

Operating Conditions

• Supply Voltage Range: 5 V to 15 V
• With a 5 V supply, output levels are TTL-compatible

Simplified schematic of an NE555

NE555 Timer Analysis from KiCad Simplified Schematic

Note: In this analysis, the RESET functionality has been excluded from the RS flip-flop. It will not be considered for this experiment.

The NE555 timer can be understood by breaking down its internal operation into four key functional blocks:

1. Voltage Divider Network
   A resistive voltage divider consisting of three equal-value resistors sets internal reference voltages at one-third (1/3) and two-thirds (2/3) of the supply voltage (VCC). These reference levels are used by the comparator stage.

2. Comparator Stage
   Two internal comparators compare external input voltages (from the threshold and trigger pins) to the reference voltages generated by the divider.

   • Comparator 1 monitors the threshold pin and compares it to 2/3 VCC.
   • Comparator 2 monitors the trigger pin and compares it to 1/3 VCC.

3. RS Flip-Flop
   The outputs of the comparators drive an internal RS flip-flop that controls the state of the output pin.

   • When the trigger falls below 1/3 VCC, the flip-flop is set, and the output goes high.
   • When the threshold exceeds 2/3 VCC, the flip-flop is reset, and the output goes low.

4. Timing Capacitor Charge/Discharge (Frequency Analysis)
   The behavior of the output depends on how the external timing capacitor (C) charges and discharges through external resistors.

   • During charging, the capacitor voltage increases toward VCC until it reaches 2/3 VCC.
   • During discharging, the voltage decreases until it falls below 1/3 VCC.
     This RC-based charging and discharging cycle defines the output waveform frequency and duty cycle, especially in astable mode.

Kicad NE555 Simplified schematic version

Voltage Divider in the 555 Timer Circuit

The voltage divider consists of three identical resistors: R1, R2, and R3, each with a value of 5kΩ. These are connected in series across a 5V DC supply. This creates two reference voltages internally within the 555 timer.

The input current into the comparator inputs of the LM358 op-amp (U1A pin 2 and U1B pin 5) is negligible — typically around 20 nA, with a maximum of a few nA.
Therefore, the same current flows through R1, R2, and R3, and the voltage drops are proportional to the resistor values.

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Voltage at Comparator Inputs

Let’s calculate the voltages at pins 5 and 2, assuming Vcc = 5V:

• Voltage at pin 5 (non-inverting input of U1B):

$$ V_+ = \left( \frac{R3}{R1 + R2 + R3} \right) \cdot V_{cc} = \left( \frac{5k}{15k} \right) \cdot 5V = 1.667 $$

• Voltage at pin 2 (inverting input of U1A):

$$ V_- = \left( \frac{R2 + R3}{R1 + R2 + R3} \right) \cdot V_{cc} = \left( \frac{10k}{15k} \right) \cdot 5V = 3.334 $$

These voltages correspond to 1/3 Vcc and 2/3 Vcc, which define the operating voltage range of the external timing capacitor C during charge and discharge.

Role in Timer Operation

These threshold voltages are used to control the capacitor voltage levels:

• When the capacitor voltage reaches 2/3 Vcc (≈ 3.334V), the upper comparator triggers a RESET signal to the flip-flop.
• When the capacitor voltage falls below 1/3 Vcc (≈ 1.667V), the lower comparator triggers a SET signal.

These signals control the output state of the internal RS flip-flop, which in turn drives the external NPN transistor T1 (e.g., 2N2222), toggling it ON (conducting) or OFF (non-conducting).

This mechanism ensures accurate switching during the charging and discharging cycles of the timing capacitor, enabling stable and predictable timing behavior.

Comparators U1A & U1B

In this experiment, the TRIG and THRES pins of the 555 timer are tied together. This configuration allows us to simulate the external timing capacitor's charge and discharge behavior using a triangular waveform (0–5 V) generated by a signal generator connected to both pins.

The waveform is offset by 2.5 V to ensure it remains entirely above ground (0 V). Alternatively, a sine wave with the same amplitude (0–5 V) and DC offset (2.5 V) can also be used.

Comparator Configuration

The comparators used are from a single AS358 IC, operating in open-loop mode. The AS358 is a low-power, dual operational amplifier that supports a wide range of single supply voltages (3 V to 36 V). Key features of the AS358 include:

• Low input bias current: typically 20 nA
• Low input offset voltage: around 2 mV

These characteristics make the AS358 well-suited for this application. In the schematic, it serves both U1A and U1B comparator roles.

Comparator Behavior

The AS358 is powered with a single 5 V supply, so its output swings between:

• High (5 V) when the non-inverting input (V⁺) is greater than the inverting input (V⁻)
• Low (0 V) when the non-inverting input (V⁺) is less than the inverting input (V⁻)

This behavior defines the logic thresholds for controlling the 555 timer's internal flip-flop based on the capacitor voltage simulation input.

Comparator U1B

• A triangular waveform is applied to the negative input (pin 6, labeled TRIG), representing the external capacitor voltage variations (displayed in yellow).

• The comparator output voltage reference at pin 7 is shown in blue.

• Two horizontal cyan lines indicate the constant voltages at 1/3 Vcc and 2/3 Vcc, generated by the voltage divider.

Operation:

• When the TRIG voltage at pin 6 is greater than 1.66 V, the comparator output goes low
  (condition: ( V_- > V_+ )).

• When the TRIG voltage falls below 1.66 V, the output goes high
  (condition: ( V_+ > V_- )),
  and the RS flip-flop enters the reset mode.

Figure 1A comparator U1B

Comparator U1A

• The THRES voltage, representing the external capacitor voltage at pin 3, controls the comparator output.

• When the THRES voltage is greater than 3.33 V, the comparator output goes high
  (condition: ( V_+ > V_- ))
  and the RS flip-flop enters the set mode.

• When the THRES voltage falls below 3.33 V, the output goes low
  (condition: ( V_+ < V_- )).

Figure 1B comparator U1A

RS flip-flop

We use the IC 74HCT02 (NOR gates) to implement the RS flip-flop.

• The base of transistor T1 is connected to the not Q output (inverted Q).
• The collector of T1 is connected to the external capacitor C (marked as DISH).

The truth table is defined below. Note that the condition R = 1 and S = 1 is invalid.

S (Set)	R (Reset)	Q (Output)	Not Q (Q̅)	Description
0	0	Q (no change)	Q̅ (no change)	Hold state
1	0	1	0	Set
0	1	0	1	Reset
1	1	Invalid	Invalid	Invalid condition

• When input R is high (reset mode), the RS output Q is low (and not Q is high).
  A current flows through the transistor base (transistor T1 is saturated).
  The DISH flag is connected to ground, allowing the external capacitor to discharge through the resistor RB connected to ground via the DISH flag.

• When input S is high (set mode), the RS output Q goes high (and not Q is low).
  The transistor T1 is off (open), so the DISH flag is disconnected.
  The external capacitor charges through resistors R1 and R2 connected to Vcc (+5 V).

As illustrated in Figures 1A and 1B, the comparator outputs never reach +5 V simultaneously, preventing the flip-flop from entering an invalid state (where outputs Q and not Q would be undetermined).

Frequency Analysis (Time Period and Frequency)

At $t = 0$, the external capacitor $C$ is discharged, so $U_C = 0,V$.
The trigger potential $\mathrm{TRIG}$ is equal to the voltage across the capacitor, thus $\mathrm{TRIG} = 0,V$.
The comparator $U1B$ output is high (see Figure 1A), and the RS flip-flop output $\overline{Q}$ is low. The transistor $T1$ is open, and the capacitor begins charging from 0 V to $\frac{2}{3} V_{cc}$ through the resistors $R_1$ and $R_2$.

When the voltage across the capacitor $U_C$ exceeds $\frac{2}{3} V_{cc}$, the comparator $U1A$ output switches high (+5 V). This causes the RS flip-flop output $\overline{Q}$ to go high, which drives current into the transistor base, saturating the transistor. As a result, the threshold node $\mathrm{THRES}$ is connected to ground.

With $\mathrm{THRES}$ grounded, the capacitor discharges through resistor $R_2$, and the voltage $U_C$ decreases exponentially until it reaches $\frac{1}{3} V_{cc}$.

When $U_C$ falls below $\frac{1}{3} V_{cc}$, the comparator $U1B$ triggers the RS flip-flop again, setting $\overline{Q}$ low. This opens the transistor and forces the capacitor to charge again through $R_1$ and $R_2$, repeating the cycle.

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The time constants during charging and discharging are:

• Discharging through $R_2$:

$$ \tau_{\text{discharge}} = R_2 C $$

$$ \tau_{\text{charge}} = C (R_1 + R_2) $$

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During charging, the voltage across the capacitor follows:

$$ \frac{2}{3} V_{cc} = V_{cc} \left(1 - e^{-t_0/\tau_{\text{charge}}} \right) $$

Solving for $t_0$:

$$ t_0 = -\tau_{\text{charge}} \ln \left(1 - \frac{2}{3}\right) = -\tau_{\text{charge}} \ln \left(\frac{1}{3}\right) = \tau_{\text{charge}} \times 1.10 $$

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During discharging, the voltage follows:

$$ \frac{1}{3} V_{cc} = \frac{2}{3} V_{cc} \times e^{-t_1/\tau_{\text{discharge}}} $$

Solving for $t_1$:

$$ t_1 = -\tau_{\text{discharge}} \ln \left(\frac{1/3}{2/3}\right) = -\tau_{\text{discharge}} \ln \left(\frac{1}{2}\right) = \tau_{\text{discharge}} \times 0.693 $$

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The total period $T$ is the sum of charging and discharging times:

$$ T = t_0 + t_1 = C (R_1 + R_2) \times 1.10 + R_2 C \times 0.693 $$

Approximating constants and combining terms:

$$ T \approx 0.7 C (R_1 + 2 R_2) $$

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The frequency is the inverse of the period:

$$ f = \frac{1}{T} = \frac{1}{0.7 C (R_1 + 2 R_2)} $$

Output driver duty cycle:

$$ \text{Duty cycle} = \frac{t_0}{t_0 + t_1} = \frac{R_B}{R_1 + 2 R_B} $$

Output waveform duty cycle:

$$ \text{Duty cycle} = \frac{t_1}{t_0 + t_1} = 1 - \frac{R_2}{R_1 + 2 R_2} $$

Low to high ratio:

$$ \frac{t_0}{t_1} = \frac{R_2}{R_1 + R_2} $$

Figure 2 illustrates the charging and discharging behavior of the external capacitor $$( C )$$ between the voltage levels $$( \frac{1}{3} V_{cc} )$$ (cursor a) and $$( \frac{2}{3} V_{cc} )$$ (cursor b).

During the charging phase, the capacitor voltage rises from cursor a at $$( \frac{1}{3} V_{cc} )$$ up to cursor b at $$( \frac{2}{3} V_{cc} )$$.
During the discharging phase, the voltage decreases from cursor b down to cursor a again, completing the cycle.

figure 2

Below is the output of comparator $$( U1B )$$ (real) when the capacitor voltage $$( U_C )$$ falls below $$( \frac{1}{3} V_{cc} )$$.
The transition from low to high state is very brief because $$( U_C )$$ remains below $$( \frac{1}{3} V_{cc} )$$ for only a short time, as the capacitor immediately begins charging again.

figure 3

Below is the output of comparator $$( U1A )$$ (real) when the capacitor voltage $$( U_C )$$ rises above $$( \frac{2}{3} V_{cc} )$$.
The transition from low to high is very brief because the condition $$( U_C &gt; \frac{2}{3} V_{cc} )$$ holds true for only a short time, as the capacitor starts discharging immediately once the peak is detected by the RS flip-flop.

figure 4

figure 5 RS flipflop output (+5v, T1 is closed and C discharge through $$R_2$$)

figure 6 inverted signal from the RS flip-flop (in our experiment we are using a NOR gate to invert the signal)

Components values for the above experiment

R1 = 1 kΩ
R2 = 7 kΩ (* by replacing R2 with a potentiometer, you can adjust frequency and duty cycle)
C = 10 μF
t₀ = 0.0559 ms
t₁ = 0.049 ms
T = 0.10499 ms
f = 9.5 Hz
Output driver duty cycle = 0.5504
Output waveform duty cycle = 0.4495
Low to high ratio = 1.224

As you can see, the duty cycle depends directly on $$( R_1 )$$ and $$( R_2 )$$.

The low-time and high-time can be approximated as:

$$ T_L = 0.7 \times C \times (R_1 + R_2) $$

$$ T_H = 0.7 \times C \times R_2 $$

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The schematic below proposes a duty cycle of 50%, where:

$$ T_L = T_H $$