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Four-digit combination lock in VHDL on an Intel MAX 10 (DE10-Lite): keypad entry, 7-segment display, comparator, lockout.

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Access Code Lock

VHDL · Intel MAX 10 (DE10-Lite) · Quartus

A digital combination lock implemented in VHDL on an Intel MAX 10 (DE10-Lite) board: a 4×4 matrix keypad enters the code, a 7-segment display echoes each keypress, and a comparator decides whether the door opens. Green LED for access granted, red LED for denied.

Pure RTL — no soft CPU, no vendor IP for the logic blocks.


Behaviour

  1. The keypad decoder scans the 4×4 matrix and emits a debounced key event.
  2. Each key is shown on the 7-segment display as it is pressed.
  3. The comparator checks the entered value against the code stored in a VHDL constant.
  4. Match → green LED (lock opens) · mismatch → red LED (access denied).

Default code: 0101 (binary 5). Change the CODE constant in comparateur.vhd to reprogram it.


Design blocks

Entity File Role
Keypad decoder decode_clavier.vhd Column scan, debouncing, key code output
7-segment driver segments.vhd BCD → segment patterns, common cathode assumed
Comparator comparateur.vhd Holds the reference code, compares the entry, drives the result
Top level serrure.qpf / serrure.qsf Quartus project, device and pin assignments
Schematics *.bdf Block-level wiring of the entities

Simulation inputs and results are stored as Quartus waveform files (*_sim.vwf, serrure.vwf).


Build & simulate

  1. Open serrure.qpf in Quartus Prime.
  2. Assign the DE10-Lite pins in the Pin Planner (keypad rows/columns, 7-segment segments, LEDs) and re-run the fitter.
  3. Compile, then program the board over USB-Blaster.
  4. To simulate, open the matching .vwf, run the functional simulation, and compare against the expected outputs.

Notes and limits

  • The design assumes a common-cathode display; invert the segment patterns for common-anode hardware.
  • db/, incremental_db/ and output_files/ are Quartus build artefacts. They are committed here for reproducibility of a specific fit; they can be regenerated and should normally be gitignored.
  • No lockout after repeated failed attempts, no timing side-channel protection — this is a teaching design of the RTL, not a certified access-control product.

Stack: VHDL · Intel MAX 10 (DE10-Lite) · Quartus Prime · ModelSim/Questa


License

MIT — see LICENSE.

About

Four-digit combination lock in VHDL on an Intel MAX 10 (DE10-Lite): keypad entry, 7-segment display, comparator, lockout.

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