intel-max10

24-hour digital clock in VHDL for the Terasic DE10-Lite (Intel MAX 10), displayed on the board's six seven-segment displays with hour/minute set inputs.

Developed a fully functional chess game on an Intel MAX10 FPGA using System Verilog. The game runs on a VGA monitor at 640×480, accepts input via a matrix keypad, enforces all official chess rules in hardware, and renders the board and pieces procedurally at the pixel level all without a soft-core processor or external memory.

Caesar cipher encoder/decoder in Verilog on an Intel MAX 10 FPGA (DE10-Lite). A finite state machine takes input from the board's switches and push buttons and shows each 6-letter word on six 7-segment displays.

Synthesizable VHDL-2008 IP cores for the Terasic DE10-Lite (MAX 10): UART with 16x oversampling, SPI master (all 4 modes), FIFO, PWM, 7-segment, BCD clock, FSM code lock. Self-checking GHDL testbenches, a board-level system test and mutation testing.

F1 starting light reaction timer on Intel MAX10 FPGA. SystemVerilog FSM, LFSR random delay, hierarchical clock management. Imperial College London (Grade: A).

Four-digit combination lock in VHDL on an Intel MAX 10 (DE10-Lite): keypad entry, 7-segment display, comparator, lockout.

Verilog implementation of an integer square root FSM and dual M9K RAM system on the Intel MAX10 FPGA, verified in ModelSim and demonstrated on the DE10-Lite board.

TCC: autocorrelação em VHDL na FPGA MAX 10 (DE10-Lite) para medição de velocidade por ultrassom, com ponto flutuante IEEE 754 e Nios II (UTFPR, 2022)

Real-time digital spirit level on the DE10-Lite FPGA (VHDL). Reads the ADXL345 accelerometer over I2C and shows tilt on the seven-segment displays and an LED bar graph. IIT Goa EE232 project.

FPGA-based single-phase SPWM sine-wave inverter using an Intel MAX 10, VHDL, H-bridge power stage, step-up transformer, and experimental validation at 120 V RMS / 60 Hz.