amba-ahb

Here are 4 public repositories matching this topic...

Ashish181104 / AMBA-AHB-Single-Master-4-Slave-Interconnect

AMBA AHB Protocol implementation in Verilog with Single Master and Four Slaves including Decoder, Multiplexer, FSM based Master, Memory Mapped Slaves and Testbench Verification.

fpga hardware verilog xilinx vivado soc xilinx-fpga digitaldesign ahb rtl-design amba-ahb

Updated Jun 5, 2026
Verilog

Saad1507 / amba-ahb-lite-interconnect

Star

AMBA AHB-Lite interconnect implementation in Verilog

hardware verilog rtl-design amba-ahb soc-interconnect

Updated Aug 23, 2026
Verilog

harinisubbiah / Leon3_Processor_WithGRETH_Verfication

Star

Functional Verification, ASIC Synthesis and Formal Verification of an AMBA Memory Interface Bridge integrated with the LEON3 Processor and GRETH Ethernet MAC.

asic software-testing formal-verification leda amba-apb design-compiler amba-ahb standalone-testing bridge-module

Updated Jun 28, 2026
C

DerathThutaram / ahb-apb-bridge-verification

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SystemVerilog testbench for verifying AMBA AHB-to-APB bus protocol bridge

systemverilog uvm apb-bridge design-verification amba-ahb

Updated Aug 26, 2026
SystemVerilog

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